An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

Thangkhiew, Phrangboklang Lyngton; Zulehner, Alwin; Wille, Robert; Datta, Kamalika; Sengupta, Indranil

doi:10.1016/j.vlsi.2019.11.014

Cited by 16 publications

(65 citation statements)

References 20 publications

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“…Memristors are solid–state-devices where the resistance can be controlled by voltage, retaining the resistance value without power consumption, and that can be used as storage devices [ 7 , 8 , 9 ]. With the application of an external voltage, the memristor can be switched back and forth between a low resistance state (LRS) and a high resistance state (HRS).…”

Section: Introductionmentioning

confidence: 99%

Resistive Switching in Electrodeposited Prussian Blue Layers

et al. 2020

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Prussian blue (PB) layers were electrodeposited for the fabrication of Au/PB/Ag stacks to study the resistive switching effect. The PB layers were characterized by different techniques to prove the homogeneity, composition, and structure. Electrical measurements confirmed the bipolar switching behavior with at least 3 orders of magnitude in current and the effect persisting for the 200 cycles tested. The low resistance state follows the ohmic conduction with an activation energy of 0.2 eV.

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Section: Introductionmentioning

confidence: 99%

Resistive Switching in Electrodeposited Prussian Blue Layers

et al. 2020

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“…These additional steps, memristors required for the data‐arrangement purposes are not included in the step, MC results for the benchmark circuits in [10, 11]. However, both the present work and the existing works in [13] provide a cumulative estimation of the steps, memristors—as involved in logic computation and data‐arrangement for the BDD‐based logic‐realization using memristors.…”

Section: Resultsmentioning

confidence: 99%

“…On the contrary, the step, memristor data shown in Table 7 for the present work, as also for the existing works in Ref. [13], represent the cumulative information for steps, memristors as needed for both logic‐computing and data arrangements. The energy‐data provided for the present work in Table 7 include the energies for both logic‐computations and data‐arrangements.…”

Section: Resultsmentioning

confidence: 99%

“…However, unlike Ref. [13], in this work, we only directly write S′ in the respective memristor inside the 3 × 3 crossbar, instead of performing MAGIC‐NOT (S) at the time of mapping of each BDD‐node (see Table 4 and Figures 3 and 4a).…”

Section: Proposed and Existing Memristive‐mappings Of A Bdd‐node Desmentioning

confidence: 99%

“…of 3 × 3 crossbar‐slices, steps, memristors, and energy required for the memristive‐realization of an input benchmark function inside a cluster of 3 × 3 crossbar‐slices using our improved synthesis technique are given as follows: Total no. of 3 × 3 crossbar‐slices required = Maximum node‐count among all the BDD‐Levels + Maximum outgoing complemented edge‐count among all the BDD‐levels, without repetition. SC = Total BDD‐Levels × SC for a single memristive‐MUX design + Index to indicate the presence of outgoing complemented‐edge in the topmost BDD‐level × 2.[SC for IMPLY‐based mapping of 2:1 MUX [10] = 11; SC for MAGIC‐based mapping of 2:1 MUX [13] = 7; SC for the proposed MAGIC‐based mapping of 2:1 MUX (Figure 3) = 6]—see Tables 2–5. MC = Total no. of 3 × 3 crossbar‐slices required * {MC for a single memristive‐MUX design + 1 memristor is considered for NOT‐operation} + 2 extra memristors to store logic ‘1’, ‘0’.[MC for IMPLY‐based mapping of 2:1 MUX [10] = 6; MC MAGIC‐based mapping of 2:1 MUX [13] = 8; MC for the proposed MAGIC‐based mapping of 2:1 MUX (Figure 3) = 7]—see Tables 2–5. Computational‐energy = Total no.…”

Section: Improved Logic Synthesis Using Existing/proposed Memristive‐mentioning

confidence: 99%

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Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

Chakraborty

Maurya

Prasad

et al. 2020

IET Computers & Digital Tech

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Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functions has been reported, where an input Boolean function is first represented as a Binary Decision Diagram (BDD), followed by the mapping of the BDD‐nodes (netlists of 2‐input NOR and NOT gates) inside a cluster of sliced crossbar‐arrays. The authors propose to map the BDD‐nodes for any input Boolean function to the crossbar‐slices using an improved technique, where each BDD‐node is mapped more efficiently, and the node‐logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping‐based realization of a BDD‐node has superior performance and energy‐efficiency than the existing IMPLY and MAGIC‐based BDD‐node designs techniques, provided all three node‐designs are implemented inside the similar‐sized crossbars. Comparative‐study of the synthesis results showed that the memristive‐circuits generated using our proposed technique are 26.95% faster, and need 42.32% lesser memristors (on average) than their peers, implemented using the existing approach of slicing crossbar‐architecture.

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