An efficient implementation of floating point multiplier

Al-Ashrafy, Mohamed; Salem, Ashraf; Anis, Wagdy R.

doi:10.1109/siecpc.2011.5876905

Cited by 51 publications

(31 citation statements)

References 4 publications

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“…This necessitates a design that produces consistent results for all the possible test cases of inputs. Since a floating point number consists of 3 parts-sign, exponent and mantissa, calculations for all the parts are carried out separately .The sequential operations involved in the computation [5] is Track 1 : Advanced Computing -100 shown in Fig. 3.A bias of 127 is used for the exponent of 8 bits , in the format as in [6].…”

Section: A Floating Point Multipliermentioning

confidence: 99%

Area and time optimized realization of 16 point FFT and IFFT blocks by using IEEE 754 single precision complex floating point adder and multiplier

Batra¹,

Kamath²,

Mohith³

et al. 2015

2015 International Conference on Soft Computing Techniques and Implementations (ICSCTI)

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Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) act as primary blocks in most of the digital signal processing applications. These two operations have undergone numerous advancements in terms of software implementation. However, there is a dearth of hardware implementation of the same, due to the involvement of floating point complex numbers. Existing Fast Fourier Transform /Inverse Fast Fourier Transform implementations mostly deal with integer data only and are incompatible with floating point data. The need of the hour is a design that can operate on floating point numbers and also achieves maximum efficiency, minimum hardware utilization and high data precision. This paper proposes implementation of a novel complex floating point arithmetic operations namely addition and multiplication. The proposed floating point adders and multipliers are used in developing 16 point Fast Fourier Transform and Inverse Fast Fourier Transform blocks. The proposed design eliminates hardware redundancy by intelligently manipulating the inputs and there by reduces the area required for implementation. The existing design and proposed design of the complex floating point multiplier is compared on the Cadence platform. Analysis of the obtained results show that the proposed design of the complex floating point multiplier as compared to the existing design, is optimal in terms of number of cells, number of gates, path delay, cell area and produces highly precise results.

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Section: A Floating Point Multipliermentioning

confidence: 99%

Area and time optimized realization of 16 point FFT and IFFT blocks by using IEEE 754 single precision complex floating point adder and multiplier

Batra¹,

Kamath²,

Mohith³

et al. 2015

2015 International Conference on Soft Computing Techniques and Implementations (ICSCTI)

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“…So it is essential to seek out an option to feed binary numbers directly as input for these applications. By using this method the time is save and the method is easier, in current situation, this is unattainable, because within this adder/subtraction, input ought to lean in IEEE 754 format [3]. In floating point data format single precision consists of 32 bits and double precision consists of 64 bits.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Multimode Single Precision Floating Point Arithmetic Unit Using Verilog

saraswat

Malik²

2017

ijsrm

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Abstract-This Paper Presents a Design and Analysis of Multimode Single Precision Floating PointArithmetic Unit Using VERILOG Hardware Description Language on FPGA. The multimode floating point arithmetic unit have addition, subtraction, multiplication and division operations. The device used is Zed Board Zynq Evaluation and Developed Kit (xc7z020clg484-1) on which the proposed design will be physically verified. We design and analyse the efficient multimode floating point arithmetic unit for IEEE 754 floating point number system, which gives a better implementation in terms of area of hardware. We have four separate units for four different arithmetic operations, by combining addition and subtraction unit into one and multiplication and division unit into one and by efficient optimization. The result of this combination is to reduce the number of LUTs used in FPGA. Thus the total area of hardware required will be reduced. The LUTs reduction is 14% and area reduction is 19%.

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“…In many signal and computer applications, high output of the arithmetic operations is needed to achieve the required performance [12]. By reducing the time delay and the amount of power consumed we can meet the requirements of many applications [3].…”

Section: Introductionmentioning

confidence: 99%