An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs

Salkhordeh, Reza; Hadizadeh, Mostafa; Asadi, Hossein

doi:10.1109/tpds.2018.2883745

Cited by 11 publications

(7 citation statements)

References 40 publications

(36 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Based on the estimation of the latency over a lifetime vs threshold curve, the optimal threshold could be selected. A Threelevel I/O Cache Architecture (TICA), which aims to improve the performance and power consumption of SSD-based I/O caching while having minimal impact on the endurance, was presented in [99]. TICA employs Read-Optimised SSD (RO-SSD), Write-Optimised SSD (WO-SSD), and DRAM as three levels of cache memory.…”

Section: G Cachementioning

confidence: 99%

Survey of Memory Management Techniques for HPC and Cloud Computing

Pupykina

Agosta

2019

IEEE Access

View full text Add to dashboard Cite

The emergence of new classes of HPC applications and usage models, such as real-time HPC and cloud HPC, coupled with the increasingly heterogeneous nature of HPC architectures, requires a renewed investigation of memory management solutions. Traditionally, memory is shared by an operating system using segmentation and paging techniques. At the same time, new classes of applications require Quality of Service (QoS) guarantees. As such, the typical practice of reserving a subset of the supercomputer to a single application becomes less attractive, leading to the exploration of cloud technologies. In this context, a viable scenario is that of multiple applications, with different QoS levels, coexisting on the same deeply heterogeneous HPC infrastructure and sharing resources. However, for this scenario to succeed in practice, resources, including memory, need to be allocated with a vision that includes both the application requirements and the current and future state of the overall system. In this survey, challenges of memory management in HPC and Cloud Computing, different memory management systems and optimisation techniques to increase memory utilisation are discussed in detail. INDEX TERMS Clouds, high performance computing, memory management, resource management. ANNA PUPYKINA received the higher education degree in data processing and control systems engineering from Samara State Aerospace University, Russia, in 2009. She is currently pursuing the Ph.D. degree with the Politecnico di Milano, under the supervision of Prof. G. Agosta. She was with Russian State Humanitarian University (RSUH), Togliatti, and also with the Department of Applied Mathematics and Informatics, Togliatti State University (TSU). Her main research interests include runtime management algorithms and programming model extensions for deeply heterogeneous systems. GIOVANNI AGOSTA received the Laurea degree in computer engineering and the Ph.D. degree in information technology from the Politecnico di Milano, Italy, in 2000 and 2004, respectively. He is currently a tenured Researcher. He has authored more than 80 articles in international journals, conferences, and workshops. His main research interest includes compiler technology. He was a recipient of four HiPEAC Awards and three Best Paper Awards. He has been involved in eight European funded projects, since 2010, holding workpackage and task leader responsibilities. He is a Full Member of the HiPEAC Network and the Organizer of two workshops colocated with the HiPEAC Conference.

show abstract

Section: G Cachementioning

confidence: 99%

Survey of Memory Management Techniques for HPC and Cloud Computing

Pupykina

Agosta

2019

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Storage systems use Dynamic Random Access Memory (DRAM)-based buffers to mitigate the considerable latency gap between storage and main memory [1][2][3][4]. DRAM benefits from low access time, high density, and unlimited lifetime, which makes it a suitable candidate for these applications.…”

Section: Introductionmentioning

confidence: 99%

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers

Hadizadeh¹,

Cheshmikhani²,

Rahmanpour³

et al. 2022

IEEE Trans. Parallel Distrib. Syst.

Self Cite

View full text Add to dashboard Cite

Performance and reliability are two prominent factors in the design of data storage systems. To achieve higher performance, recently storage system designers use Dynamic RAM (DRAM)-based buffers. The volatility of DRAM brings up the possibility of data loss and data inconsistency. Thus, a part of the main storage is conventionally used as the journal area to be able of recovering unflushed data pages in the case of power failure. Moreover, periodically flushing buffered data pages to the main storage is a common mechanism to preserve a high level of reliability. This scheme, however, leads to a considerable increase in storage write traffic, which adversely affects the performance. To address this shortcoming, recent studies offer a small N on−V olatile M emory (NVM) as the P ersistent Journal Area (PJA) along with DRAM as an efficient approach to overcome DRAM vulnerability against power failure while effectively reducing storage write traffic. This approach, named N V M −Backed Buf f er (NVB-Buffer), features from advantages of NVMs and addresses DRAM shortcomings. In this paper, we employ the most promising technologies for PJA among the emerging technologies, which is Spin−T ransf er T orque M agnetic Random Access M emory (STT-MRAM) to meet the requirements of efficient PJA by providing high endurance, non-volatility, and DRAM-like latency. Despite these advantages, STT-MRAM faces major reliability challenges, i.e. Retention Failure, Read Disturbance, and Write Failure, which have not been addressed in previously suggested NVB-Buffers. In this paper, we first demonstrate that the retention failure is the dominant source of errors in NVB-Buffers as it suffers from long and unpredictable page idle intervals (i.e., the time interval between two consecutive accesses to a PJA page). Then, we propose a novel NVB-Buffer management scheme, named, Cold P age Awakening (CoPA), which predictably reduces the idle time of PJA pages. To this aim, CoPA employs Distant Ref reshing to periodically overwrite the vulnerable PJA page contents by opportunistically using their replica in DRAM-based buffer. We compare CoPA with the state-of-the-art schemes over several well-known storage workloads based on physical journaling. Our evaluations show that CoPA significantly reduces the maximum page idle time, which leads to three orders of magnitude lower failure rate with negligible performance degradation (1.1%) and memory overhead (1.2%).

show abstract

“…To alleviate the performance shortcomings of such HDDbased storage systems, enterprise manufacturers, such as Dell EMC, HP, and NetApp [3], [4], [5], and various research works on emerging storage architectures, such as [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], propose I/O caching schemes that accelerate the response 1. Due to the degraded mode of Redundant Array of Independent Disks (RAID) [31] during the rebuild process in SSDs.…”

Section: Introductionmentioning

confidence: 99%

ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms

Ahmadian

Salkhordeh

Mutlu

et al. 2021

IEEE Trans. Parallel Distrib. Syst.

Self Cite

View full text Add to dashboard Cite

In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: they support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of imposing a write operation to the SSD (to copy the data block into the cache), resulting in an even larger number of writes into the SSD. Previous I/O caching schemes on virtualized platforms only partially mitigate the endurance limitations of SSD-based I/O caches; they mainly focus on assigning efficient cache write policies and cache space to the VMs. Moreover, existing cache space allocation schemes have inefficiencies: they do not take into account the impact of cache write policy in reuse distance calculation of the running workloads and hence, reserve cache blocks for accesses that would not be served by cache.In this paper, we propose an Efficient Two-Level I/O Caching Architecture (ETICA) for virtualized platforms that can significantly improve I/O latency, endurance, and cost (in terms of cache size) while preserving the reliability of write-pending data blocks. As opposed to previous one-level I/O caching schemes in virtualized platforms, our proposed architecture 1) provides two levels of cache by employing both Dynamic Random-Access Memory (DRAM) and SSD in the I/O caching layer of virtualized platforms and 2) effectively partitions the cache space between running VMs to achieve maximum performance and minimum cache size. To manage the two-level cache, unlike the previous reuse distance calculation schemes such as Useful Reuse Distance (URD), which only consider the request type and neglect the impact of cache write policy, we propose a new metric, Policy Optimized reuse Distance (POD). The key idea of POD is to effectively calculate the reuse distance and estimate the amount of two-level DRAM+SSD cache space to allocate by considering both 1) the request type and 2) the cache write policy. Doing so results in enhanced performance and reduced cache size due to the allocation of cache blocks only for the requests that would be served by the I/O cache. ETICA maintains the reliability of write-pending data blocks and improves performance by 1) assigning an effective and fixed write policy at each level of the I/O cache hierarchy and 2) employing effective promotion and eviction methods between cache levels. Our extensive experiments conducted with a real implementation of the proposed two-level storage caching architecture show that ETICA provides 45% higher performance, compared to the state-of-the-art caching scheme...

show abstract

An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs

Cited by 11 publications

References 40 publications

Survey of Memory Management Techniques for HPC and Cloud Computing

Survey of Memory Management Techniques for HPC and Cloud Computing

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers

ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms

Contact Info

Product

Resources

About