An efficient FPGA-based implementation of Pollard's (ρ - 1) factorization algorithm

Abstract

Due to the widespread use of public key cryptosystems whose security depends on the presumed difficulty of the factorization problem, the algorithms forfinding the prime factors of large composite numbers are becoming extremely important. In recent years the limits of the best integerfactorization algorithms have been extended greatly, due in part to Moore's law and in part to algorithmic improvements. Furthermore, new silicon devices, such as FPGAs, give us the advantage of custom hardware architectures for minimizing execution time for such difficult computations. This paper demonstrates a very efficient FPGA-based design executing Pollards (p -1) factorization algorithm. The proposed device offers a speedupfrom 20 to 231 when compared to the software implementation ofthe same algorithm in a state-of-the-art CPU.