An Efficient Flexible Common Operator for FFT and Viterbi Algorithms

Versatile digital architecture for mobile terminal

“…To give a real evaluation of the performance and complexity of the proposed architecture, we compare our implementation results with previous works that share some common target functionality with the one of the paper [5,9,12]. The comparison between common operators (reconfigurable cells) based on different architectures and/or implemented in different technologies is not straightforward.…”

“…The comparison between common operators (reconfigurable cells) based on different architectures and/or implemented in different technologies is not straightforward. For this reason, as neither [9] nor [12] are implemented FPGA technology, we have implemented these previous works in the FPGA Virtex 5 using VHDL to compare directly our all results with these previous architectures, and with same metrics which give the resources consumption and maximum frequency for different precisions (word-lengths). Figs.…”

“…It is just juxtaposition of several standard chains and the ''re-configuration'' is simply performed by a switch from one to another. Moreover, its scalability is limited by the standards considered and the complexity of its implementation remains maximum [7][8][9]. For instance, [7] proposes to compare its reconfigurable architecture with the Velcro technique using the Gain in terms of ALUTs, the critical path delay in nanoseconds, the memory saving and performance-to-cost ratio ''g'' defined by 1/(TC)*10 6 , where C is the number of logic blocks related to the cost of a FPGA-based circuit while T the execution time in nanoseconds (ns).…”

“…On the other hand, the use of the Common Operator enables to reduce the number implemented operators because of the 'reuse' across the algorithms, rather than just across standards [10]. Thereby, these solutions are not efficient (cost and size) [7,9,10] because they do not take into account the possible RTL optimization architecture synthesis. Indeed, one optimization process of the architectural synthesis technique is the common operators (CO) or sharing functions (SF) technique which may reduce the implementation logic area for producing a optimized design suitable for embedded applications, was introduced in [2,3].…”

“…Many previous works have proposed various implementations of generic architectures. For instance, the authors in [9,10] propose Common Operators (CO) between the FFT (Fast Fourier Transform) and Forward error correction (FEC) decoding. In [11], authors propose a processing unit that performs the multiply accumulate operation in the Rake mode and butterfly operations in the FFT Mode while in [12] a reconfigurable processing Fig.…”