An Efficient Fault Detection Method for Elliptic Curve Scalar Multiplication Montgomery Algorithm

Bedoui, Mouna; Bouallègue, Belgacem; Hamdi, Belgacem; Machhout, Mohsen

doi:10.1109/dtss.2019.8914743

Cited by 6 publications

(3 citation statements)

References 10 publications

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“…To protect against these attacks, we used a countermeasure at a higher hierarchical level of cryptography on elliptic curves, which is scalar multiplication and can therefore be used on any elliptic curve that we proposed in our paper [35]. The proposed fault detection method is based on scrambling technique.…”

Section: Proposed Fault Detection Scheme For the Ecdsa Implementationsmentioning

confidence: 99%

“…Figure 6: Technique of scrambling in Scalar Multiplication block [35] Our design for hardware implementation of ECDSA digital signature with and without fault detection method for Montgomery scalar multiplication, was simulated, synthesized, and implemented using XC5VFX70T board from Xilinx Virtex-5 family. In addition, the developed method has been examined practically as shown in Fig.…”

Section: Proposed Fault Detection Scheme For the Ecdsa Implementationsmentioning

confidence: 99%

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A Secure Hardware Implementation for Elliptic Curve Digital Signature Algorithm

Bedoui¹,

Bouallègue²,

Ahmed³

et al. 2023

Computer Systems Science and Engineering

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Since the end of the 1990s, cryptosystems implemented on smart cards have had to deal with two main categories of attacks: side-channel attacks and fault injection attacks. Countermeasures have been developed and validated against these two types of attacks, taking into account a well-defined attacker model. This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm (ECDSA) algorithm. The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks. More precisely, we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key. ECDSA can be implemented in different ways, in software or via dedicated hardware or a mix of both. Many different architectures are therefore possible to implement an ECDSA-based system. For this reason, this work focuses mainly on the hardware implementation of the digital signature ECDSA. In addition, the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinx field programmable gate arrays (FPGA) platform (Virtex-5). Our implementation results have been compared and discussed. Our area, frequency, area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA.

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Section: Proposed Fault Detection Scheme For the Ecdsa Implementationsmentioning

confidence: 99%

Section: Proposed Fault Detection Scheme For the Ecdsa Implementationsmentioning

confidence: 99%

A Secure Hardware Implementation for Elliptic Curve Digital Signature Algorithm

Bedoui¹,

Bouallègue²,

Ahmed³

et al. 2023

Computer Systems Science and Engineering

Self Cite

View full text Add to dashboard Cite

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“…In this study, we suggest an innovative design for an areaefficient FFT by reusing 𝑁/2 numbers of butterfly units more than once rather than employing (𝑁/2) log 2 𝑁 butterfly units only once [11]. This is accomplished via a time control unit that recycles the butterfly units to finish the FFT calculation after sending back the data that it had previously calculated for 𝑁/2 butterfly units to itself for (log 2 𝑁 ) times.…”

Section: Objectivementioning

confidence: 99%

A Brand-New, Area - Efficient Architecture for the FFT Algorithm Designed for Implementation of FPGAs

Swetha

Sandi

2023

IJRITCC

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Elliptic curve cryptography, which is more commonly referred to by its acronym ECC, is widely regarded as one of the most effective new forms of cryptography developed in recent times. This is primarily due to the fact that elliptic curve cryptography utilises excellent performance across a wide range of hardware configurations in addition to having shorter key lengths. A High Throughput Multiplier design was described for Elliptic Cryptographic applications that are dependent on concurrent computations. A Proposed (Carry-Select) Division Architecture is explained and proposed throughout the whole of this work. Because of the carry-select architecture that was discussed in this article, the functionality of the divider has been significantly enhanced. The adder carry chain is reduced in length by this design by a factor of two, however this comes at the expense of additional adders and control. When it comes to designs for high throughput FFT, the total number of butterfly units that are implemented is what determines the amount of space that is needed by an FFT processor. In addition to blocks that may either add or subtract numbers, each butterfly unit also features blocks that can multiply numbers. The size of the region that is covered by these dual mathematical blocks is decided by the bit resolution of the models. When the bit resolution is increased, the area will also increase. The standard FFT approach requires that each stage contain times as many butterfly units as the stage before it. This requirement must be met before moving on to the next stage.

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