An efficient dynamically reconfigurable on-chip network architecture

Modarressi, Mehdi; Sarbazi-Azad, Hamid; Tavakkol, Arash

doi:10.1145/1837274.1837316

Cited by 31 publications

(12 citation statements)

References 8 publications

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“…VOPD and MWD applications have been considered for the simulations, whose topologies have been taken from [5]. The applications use the same set of IPCores but the traffic pattern among the cores is different for each different application.…”

Section: Resultsmentioning

confidence: 99%

Topology Re-Configuration for On-Chip Networks with Back-Tracking

VenkataTheertha¹,

Nandi²,

Bharathi³

2013

IJCA

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Supporting multiple applications is a critical feature of an NoC when several different applications are integrated into a single modern and complex multi-core system-on-chip or chip multiprocessor. In this paper, a novel reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented with backtracking which provides guaranteed throughput is presented. The proposed NoC supports multiple applications by configuring its topology to the topology which matches the input application and also supports a dead-and-live lock free dynamic path set-up scheme. The re-configurability can be achieved by changing the inter-router connections to some predefined configuration corresponding to the application. This increases the support for higher number of applications which further increases the traffic congestion leading to path blockages and substantially to data loss. To manage the blockages and to support a dead and live lock free dynamic path set-up scheme we go for back-tracking. This can be achieved with an efficient and proper design of on-chip switching nodes. This paper first introduces the proposed reconfigurable topology and then deals with the back-tracking feature. Finally the architecture is valuated for power and area.

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Section: Resultsmentioning

confidence: 99%

Topology Re-Configuration for On-Chip Networks with Back-Tracking

VenkataTheertha¹,

Nandi²,

Bharathi³

2013

IJCA

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“…If regular network is not provided, programmers need to optimize the application according to the irregular network topology [12], [13] or customize the network topology to match the traffic pattern of the application [14], [15], [16], [17], in order to fully exploit the processing capabilities. This is a big burden for programmers because an optimized program for one network may not work well for a different one and the programmers are facing various irregular networks as the faults occur randomly and cannot be predicted.…”

Section: Introductionmentioning

confidence: 99%

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

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With the increased density of three-dimensional (3D) processor arrays, faults can potentially occur quite often due to power overheating during massively parallel computing. In order to achieve fault-tolerance under such a scenario, an effective way is to find an as large as possible logical fault-free subarray of m 0 Â n 0 Â h 0 from a faulty array of m Â n Â h (m 0 m; n 0 n; h 0 h), such that an original application can still work on the m 0 Â n 0 Â h 0 subarray. This paper investigates the problem of constructing maximum fault-free subarrays with minimum interconnection length from 3D arrays with faults. First, we prove that constructing maximum logical array (MLA) is NP-complete. We propose a linear-time algorithm which is capable of producing an MLA for the problem with the constraint of selected indexes. Second, we prove that minimizing the interconnection length (inter-length) of the MLA is NP-hard. We propose an efficient heuristic which significantly reduces the inter-length by revising each logical plane of the MLA. This leads to the reduction of communication cost, capacitance and dynamic power dissipation. In addition, we propose a lower bound for the inter-length of the MLA to evaluate the proposed algorithms. Simulation results show that, the size of logical array can be improved up to 62.6 percent in average, and the inter-length redundancy can be reduced by 22.7 percent in average, compared to the state-of-the-art, for all cases considered.Index Terms-3D processor array, fault tolerance, maximum logical array, interconnection length, NP-complete problem, algorithm Ç G. Jiang is with the

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“…Some works [Stensgaard and Sparso 2008;Modarressi and Sarbazi-Azad 2007;Modarressi et al 2010Modarressi et al , 2011Avakian et al 2010;Wu et al 2011;Elmiligi et al 2007;Kunert et al 2007;Zheng et al 2010;Rana et al 2009; Bartic et al 2003Bartic et al , 2005Ahmed et al 2006] configure the network to meet application constraints. A reconfigurable NoC (ReNoC) architecture has been presented in Stensgaard and Sparso [2008] which enables the network topology to be configured by the application running on the SoC by using topology switches.…”

Section: Introductionmentioning

confidence: 99%

“…A reconfigurable NoC (ReNoC) architecture has been presented in Stensgaard and Sparso [2008] which enables the network topology to be configured by the application running on the SoC by using topology switches. A core mapping mechanism for reconfigurable NoC architectures has been presented [Modarressi and Sarbazi-Azad 2007;Modarressi et al 2010;Modarressi et al 2011], where reconfiguration is achieved via programmable switches in the network. The reconfigurability allows NoC to dynamically tailor its topology to the traffic pattern of different applications.…”

Section: Introductionmentioning

confidence: 99%

Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration

Soumya

Sharma

Chattopadhyay

2014

ACM Trans. Reconfigurable Technol. Syst.

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This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The area overhead for this local reconfiguration has been shown to be very small. We have also presented the strategy to map the cores of an application set onto this architecture. This has been achieved via a two-phase procedure. In the first phase, the cores of the combined application set are mapped tentatively to individual routers, minimizing the communication cost. In the second phase, for each application, positions of individual cores are finalized. A core gets attached to any neighbor of its tentative allocation. We have proposed Integer Linear Programming (ILP) formulation of both the phases. Since ILP takes large amount of CPU time, we have also formulated a Particle Swarm Optimization (PSO)-based solution for the two phases. A heuristic approach has also been developed for the reconfiguration. Comparison of communication cost, latency and network energy have been carried out for the applications, before and after reconfiguration. It shows significant improvement in performance via reconfiguration.

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An efficient dynamically reconfigurable on-chip network architecture

Cited by 31 publications

References 8 publications

Topology Re-Configuration for On-Chip Networks with Back-Tracking

Topology Re-Configuration for On-Chip Networks with Back-Tracking

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration

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