An efficient design and comparative analysis of low power memory cell structures

Gavaskar, K.; Ragupathy, U. S.

doi:10.1109/icgccee.2014.6922280

Cited by 13 publications

(3 citation statements)

References 13 publications

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“…The V th of a MOSFET is the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. Low Vth devices switch faster, and are therefore helpful on critical delay paths to minimize clock periods [13]. The consequence is that low Vth devices have considerably higher static leakage power.…”

Section: Proposed Circuit Using Mtcmos Techniquementioning

confidence: 99%

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Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Gavaskar¹,

Thangaraj²

2019

IJCA

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SRAM is faster and more expensive and it is typically used for CPU cache. SRAMs are the fastest form of RAM available which does not need to be refreshed periodically. Here, 6T SRAM cell with O-ABB circuit is designed. On-chip adaptive body bias (O-ABB) circuit consists of standby leakage current (Iddq) sensor circuit, decision circuit and body bias control circuit which are used to compensate the effect of NBTI. Dynamic power is the power measured when circuit is in active mode. Here, Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technology is applied in the individual circuit of On-chip adaptive body bias to decrease the power. Low power MTCMOS methodology is applied in the proposed circuit which provides high performance and low power design. Design metrics such as Power, Delay and Power delay product are taken in to account. After applying MTCMOS technology, the power and the power delay product of the proposed circuit decreases when compared the existing circuit. All the circuits were designed using SYNOPSYS EDA tool and simulated in 28nm technology.

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Section: Proposed Circuit Using Mtcmos Techniquementioning

confidence: 99%

“…Reducing the total power consumption in such systems is significant since it is advantageous to maximize the run time with minimum requirements on size, battery life and weight allocated to batteries. So the most important feature to consider while designing SoC for moveable devices is low power design [13].…”

Section: Introductionmentioning

confidence: 99%

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Gavaskar¹,

Thangaraj²

2019

IJCA

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“…The usage of electronic devices and integrated circuits have increased in recent years because of technological advances [1]. The advancement of Complementary Metal Oxide Semiconductor (CMOS) process technology results in a smaller semiconductor system [22]. SRAM is the basic building block of most electronic devices, providing maximum performance and low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

Gavaskar¹,

Ragupathy²

2018

Analog Integr Circ Sig Process

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An efficient design and comparative analysis of low power memory cell structures

Cited by 13 publications

References 13 publications

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

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