An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications

Gavaskar, K.; Ragupathy, U. S.

doi:10.5958/2249-7315.2017.00035.1

Cited by 7 publications

(3 citation statements)

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“…Whenever a word line (WL) is activated for read or write operation, the access transistors are turned ON connecting the cell to the complementary bit line (BL) columns. Some advantages of this circuit topology are static power dissipation (SPD) is very small, medium power consumption, small leakage current, and need less time to access data [24][25].…”

Section: Sram Memorymentioning

confidence: 99%

A Review On Sram Memory Design Using Finfet Technology

Lakshmi¹,

Kamaraju²

2022

Preprint

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An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to balance the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices face some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, the memory must have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional (3D) design of the gate. FinFET has been used to improve the overall performance, which includes efficiency, power, and area. Moreover, FinFET has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies.

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Section: Sram Memorymentioning

confidence: 99%

A Review On Sram Memory Design Using Finfet Technology

Lakshmi¹,

Kamaraju²

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Whenever a word line (WL) is activated for read or write operation, the access transistors are turned ON connecting the cell to the complementary bit line (BL) columns. The most important advantage of this circuit topology is that the static power dissipation is very small, medium power consumption, small leakage current and need less time to access data (Bhaskar, 2017;Gavaskar & Ragupathy, 2017).…”

Section: Introductionmentioning

confidence: 99%

A Review on SRAM Memory Design Using FinFET Technology

Lakshmi¹,

Kamaraju²

2022

International Journal of System Dynamics Applications

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An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to compensate the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices faces some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, it is necessary for the memory to have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional design of the gate. FinFET has been used to improve the overall performance and has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies.

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“…The Propagation delay is calculated between 50% of input transition to the corresponding 50% of output transition for any gate [20]. This is the time needed for a signal to propagate through a gate or net.…”

Section: Introductionmentioning

confidence: 99%

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Gavaskar¹,

Thangaraj²

2019

IJCA

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SRAM is faster and more expensive and it is typically used for CPU cache. SRAMs are the fastest form of RAM available which does not need to be refreshed periodically. Here, 6T SRAM cell with O-ABB circuit is designed. On-chip adaptive body bias (O-ABB) circuit consists of standby leakage current (Iddq) sensor circuit, decision circuit and body bias control circuit which are used to compensate the effect of NBTI. Dynamic power is the power measured when circuit is in active mode. Here, Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technology is applied in the individual circuit of On-chip adaptive body bias to decrease the power. Low power MTCMOS methodology is applied in the proposed circuit which provides high performance and low power design. Design metrics such as Power, Delay and Power delay product are taken in to account. After applying MTCMOS technology, the power and the power delay product of the proposed circuit decreases when compared the existing circuit. All the circuits were designed using SYNOPSYS EDA tool and simulated in 28nm technology.

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An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications

Cited by 7 publications

References 0 publications

A Review On Sram Memory Design Using Finfet Technology

A Review On Sram Memory Design Using Finfet Technology

A Review on SRAM Memory Design Using FinFET Technology

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

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