An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings

Ohwada, Ayaka; Kojima, Tetsuya; Amano, Hideharu

doi:10.1109/pdp55904.2022.00010

Cited by 1 publication

(1 citation statement)

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“…However, due to the complexity of programming the hardware structure, the fuzziness or imprecision of many application dependencies, and the resulting conservative parallel task partitioning strategy, it is challenging to develop applications and fully harness the advantages of reconfigurable architecture. Reconfigurable processor compilation technology [8]- [10] can generate configuration information by automatically mining parallelism, reducing storage delays, and employing other optimization techniques. This enables all hardware resources on the array processors to work efficiently together, offering the potential to overcome the usability limitations of reconfigurable architecture [11].…”

Section: Introductionmentioning

confidence: 99%

Automatic Compilation of CNN on Reconfigurable Array Processor Based on Scalable Instruction Group Library

Li,

Wang,

Sheng

et al. 2023

IEEE Access

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Although reconfigurable architecture is an inevitable choice for dealing with high-intensive applications, the opacity of hardware structure programming and the fuzziness or imprecision of many dependencies in applications make it difficult to develop applications and take full advantage of reconfigurable architecture. In order to address these challenges, this paper proposes an automatic compilation framework based on a scalable instruction group library, using convolutional neural network (CNN) applications as an example. The proposed framework first identifies functions such as data extraction, data distribution, data summary, and data processing, and divides the reconfigurable processors into multiple logical types. Next, the calculation modes are extracted by analyzing the CNN calculation process. Based on these calculation modes, efficient assembly instruction groups are designed, constituting the scalable instruction group library. Using this library, efficient mapping for CNN applications written in high-level languages can be easily realized on reconfigurable array processors. The experimental results demonstrate that the proposed method reduces the difficulty of programming and achieves better speedup performance compared with OpenMP and LLVM parallel compilation models. Moreover, the scalability of the instruction group library provides helpful guidance for the reconfigurable implementation of domain-oriented applications.INDEX TERMS Reconfigurable architecture, reconfigurable computing, compilation techniques, CNN.

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Section: Introductionmentioning

confidence: 99%