An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

Tsukikawa, Y.; Kajimoto, Takeshi; Okasaka, Y.; Morooka, Y.; Furutani, K.; Miyata, Hiroshi; Ozaki, H.

doi:10.1109/4.280705

Cited by 18 publications

(6 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The HPC scheme consists of transfer transistor (Mn1), discharge transistor (Mp1), and auxiliary transistor (Mp2). The gate nodes of Mn1 and Mp1 are connected together from which Mp2 links to the ground rail in a diode connected configuration [6,10]. The pumping clocks, CLK1 and CLK2, are two non-overlapping clocks.…”

Section: Conventional Negative Charge Pump Circuitsmentioning

confidence: 99%

“…The Dickson charge pump [4,9] consisting of diode connected transistor and pumping capacitor is simple but has a low pumping efficiency because the threshold voltage drop in the diode connected transistor hinders charge transfer from the load to ground. To improve the pumping efficiency, a hybrid pumping circuit (HPC) [10] using NMOS and PMOS transistors is introduced. An auxiliary circuit consisting of diode connected PMOS and small capacitor provides the appropriate pumping control signal under the condition that V DD is higher than 2 times the threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

2020

View full text Add to dashboard Cite

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

show abstract

Section: Conventional Negative Charge Pump Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

2020

View full text Add to dashboard Cite

show abstract

“…To serve this purpose, back-bias voltage (VBB) generation technique has been used in high density DRAM technology. With back-bias voltage, the junction capacitance is reduced, cut-off characteristics of the access transistors are improved, and the device isolation and latch-up endurance are enhanced [1][2][3][4]. A back-bias voltage generator with a faster speed and improved current drivability is needed for future DRAM technology [5,6].…”

Section: Introductionmentioning

confidence: 99%

High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current

Yim¹,

Lee²,

Yoon³

2020

Electronics

View full text Add to dashboard Cite

Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by the increasingly difficult task of sensing cell data reliably. One of the essential methods to preserve sustainable data retention characteristic is to curtail the sub-threshold leakage current by using a negative voltage bias for the bulk of access transistors. This negative back-bias is generated by a back-bias voltage generator. This paper proposes a novel high-speed back-bias voltage (VBB) generator with a cross-coupled hybrid pumping scheme. The conventional circuit uses one fixed voltage to control the gates of discharge of the p-channel metal oxide semiconductor (PMOS) and transfer n-channel metal oxide semiconductor (NMOS), respectively. However, the proposed circuit adds an auxiliary pump, thereby able to control more aptly with a lower negative voltage when discharging and a higher positive voltage when transferring. As a result, the proposed circuit achieves a faster pump-down speed and higher pumping current at a lower supply voltage compared to conventional circuits. The H-simulation program with integrated circuit emphasis (HSPICE) simulation results with the Taiwan semiconductor manufacturing company (TSMC) 0.18 um process technology indicates that the proposed circuit has about a 20% faster pump-down speed at a supply voltage of voltage common collector (VCC) = 1.2 V and about 3% higher pumping current at VBB from −0.6 V to −1 V with the ability to generate a near 3% higher ratio of |VBB|/VCC at VCC = 0.6 V compared to conventional circuits. Hence, the proposed circuit is extremely suitable and promising for future low-power and high-performance DRAM applications.

show abstract

“…There have been many studies that have focused on the optimization of the VBB generator [4]- [6], but they have concentrated on improving the efficiency of the VBB generator itself. In [7], the VBB generator was considered according to the temperature from the view point of the latch up, but the VBB level cannot be controlled accurately by the oscillator without the detection of its level.…”

Section: Introductionmentioning

confidence: 99%

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

Son

Byun

Jun

et al. 2010

ETRI J

View full text Add to dashboard Cite

In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back-bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back-bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back-bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of -0.85 mV/℃, and its static current consumption is found to be only 0.83 μA@2.0 V. Keywords: Pseudo SRAM, memories, RCAT, temperature, back-bias voltage generator. Manuscript received June 23, 2009; revised Oct. 28, 2009; accepted Nov. 12, 2009. This work was supported by the Korea Foundation for International Cooperation of Science & Technology (KICOS) through a grant provided by the Korea Ministry of Science & Technology (MOST) (K20601000002-07E0100-00220) and of Seoul Program (10920) and was developed within the scope of Human Resource Development Project for IT SoC Architect.Jong-Pil Son (phone: +82 31 208 0695, email: jp.son@samsung.com), Young-Hyun Jun (email: yhjun.jun@samsung.com), and Kinam Kim (email: kn_kim@samsung.com) are with the Memory Division, Samsung Electronics Corporation, Hwasung, Rep. of Korea.Hyun-Geun Byun (email: hgbyun@samsung.com) is with the Department of Semiconductor, SSIT, Samsung Electronics Corporation, Yongin, Rep. of Korea.Soo-Won Kim (email: ksw@korea.ac.kr) is with the Department of Electronics Engineering, Korea University, Seoul, Rep. of Korea. doi:10.4218/etrij.10.0109.0366 I. IntroductionRecently, the density of memories for mobile applications has continuously increased with the downward scaling of process technology, but there is still a need for less power consumption and simultaneously, higher operating speed. Further scaling of the process causes short channel effects in the cell transistors and increases their leakage currents. This increased leakage makes the data retention time shorter and makes the memory consume more power. The pseudo SRAM is a memory for mobile applications using the SRAM interface with the 1T or 2T cell array of DRAM instead of the 6T SRAM cell array. Using a DRAM cell array makes the die size small and reduces the cost. However, it also requires hidden refresh operations and lower standby current because it uses the SRAM interface. The recessed channel array transistor (RCAT) pseudo SRAM that has been generally used in recent years has the advantages of lower leakage and scalability compared to the planar transistor RAM [1]- [3]. Even though the RCAT process reduces the leakage drastically, it still has several kinds of leakage that should be considered to determine the data retention time. Using the RCAT process, the cell drivability (cell saturation current) should also be considered because t...

show abstract

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

Cited by 18 publications

References 5 publications

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

Contact Info

Product

Resources

About