An Efficient Architecture for Modified Lifting-Based Discrete Wavelet Transform

Pinto, Rohan; Shama, Kumara

doi:10.1007/s11220-020-00317-z

Cited by 6 publications

(1 citation statement)

References 38 publications

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“…Lifting-based hardware architectures [ 33 , 34 , 35 , 36 , 37 , 38 ] are usually simpler, have lower computational complexity and utilize less amount of logic and memory resources. The most efficient hardware architectures of the 1-D DWT and 2-D DWT are described in [ 28 ] and [ 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 , 54 , 55 , 56 , 57 , 58 , 59 , 60 ]. The concept of the proposed 2-D DWT with 5/3 filters and its hardware architecture are presented in [ 61 , 62 , 63 ].…”

Section: Introductionmentioning

confidence: 99%

Digital Image Decoder for Efficient Hardware Implementation

Savić

Prokin

Rajović

et al. 2022

Sensors

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Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the-art realizations. The proposed digital image decoder has been implemented in a low-cost FPGA device and it has been shown that it requires at least 32% less memory resources in comparison to the other state-of-the-art decoders which can process high-definition frame size. The proposed solution also requires effectively lower memory size than state-of-the-art architectures which process frame size or tile size smaller than high-definition size. The presented digital image decoder has maximum operating frequency comparable with the highest maximum operating frequencies among the state-of-the-art solutions.

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