An efficient approach to pseudo-exhaustive test generation for BIST design

Chen, C.-I.H.; Sobelman, Gerald E.

doi:10.1109/iccd.1989.63431

Cited by 11 publications

(5 citation statements)

References 6 publications

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“…Pseudo-exhaustive approach: In pseudo-exhaustive approach, circuits are logically partitioned into smaller parts and then each part is tested exhaustively by much fewer test vectors [20][21][22][23]. Different algorithms have been proposed for circuit-partitioning in order to reduce hardware overhead and testing time [23][24][25][26].…”

Section: Techniques Of Ic Testingmentioning

confidence: 99%

Challenges and directions for testing IC

et al. 2004

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Section: Techniques Of Ic Testingmentioning

confidence: 99%

Challenges and directions for testing IC

et al. 2004

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“…Then, the same approach is applied to the remaining registers. The final solution of example 3 by using the 10,11,4) backtrack (11,8,T,4) relabeled (8,11,4) backtrack (11,10,T,4) relabeled 10,11,4) backtrack (11,7,T,4) relabeled (7,11,4 backtrack ( backtrack(11,5,T,4) relabeled (5,13,4) backtrack (13,6,T,4) relabeled (6,11,4) backtrack(ll,10,T,4) relabeled (10,11,4) backtrack (11,8,T,4) re labeled (8,11,4) backtrack (…”

Section: (That Is X2 X6 X7mentioning

confidence: 99%

“…WCP, and a variation called WCP II, were shown to produce designs requiring the fewest number of buses in large synthesis examples. These algorithms have polynomial time complexity and also yield excellent results when applied to the test generation problem of Built-In Self-Test design in [13].…”

Section: Introductionmentioning

confidence: 99%

Using PDM on Multiport Memory Allocationin Data Path

Chen

1990

VLSI Design

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A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.

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“…Step 3 [1], "SDC" [10], "LFSRs/XORs" [12], "CWC" [11], "Condensed LFSR" [14] and "LFSR with Cyclic Code" [15] Example: Consider the circuit given in Figure 4(a). In this Section, we use 42 circuits to evaluate "BISTSYN" and also compare the generated results with those produced by five previously proposed test generation methods ("SDC" [10], "LFSRs/XORs" [12], "CWC" [11], "Condensed LFSR" [14] and "LFSR with Cyclic Code" [15]).…”

Section: Introductionmentioning

confidence: 99%

“…Built-In Self-Test (BIST) has been proposed as a powerful technique for addressing the highly complex problems of VLSI testing [1][2][3][4][5][6][7][8][9]. The basic idea is to include the test generator and evaluator into the design and to perform the testing internal to the chip.…”

Section: Introductionmentioning

confidence: 99%

Partitioning Techniques for Built‐In Self‐Test Design

Chen

1990

VLSI Design

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An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, TwoPhase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.

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An efficient approach to pseudo-exhaustive test generation for BIST design

Cited by 11 publications

References 6 publications

Challenges and directions for testing IC

Challenges and directions for testing IC

Using PDM on Multiport Memory Allocationin Data Path

Partitioning Techniques for Built‐In Self‐Test Design

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