Three-dimensional IC technology enables an additional dimension of freedom for circuit design. Challenges arise for placement tools to handle the through-silicon via (TS via) resource and the thermal problem, in addition to the optimization of device layer assignment of cells for better wirelength. This chapter introduces several 3D global placement techniques to address these issues, including partitioning-based techniques, quadratic uniformity modeling techniques, multilevel placement techniques, and transformation-based techniques. The legalization and detailed placement problems for 3D IC designs are also briefly introduced. The effects of various 3D placement techniques on wirelength, TS via number, and temperature, and the impact of 3D IC technology to wirelength and repeater usage are demonstrated by experimental results.
IntroductionPlacement is an important step in the physical design flow. The performance, power, temperature and routability are significantly affected by the quality of placement results. Three-dimensional IC technology brings even more challenges to the thermal problem: (1) the vertically stacked multiple layers of active devices cause a J. Cong (B)