An efficient algorithm to reduce test power consumption by scan cell and scan vector reordering

Reddy, Karri Vivek; Chattopadahyay, S.

doi:10.1109/indico.2004.1497775

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…One of these techniques is the scan cell ordering method [13][14][15][16]. These techniques reduce the WSA by arranging the scan cells which cause more internal circuit transitions to the positions with low transition weight in the scan chain.…”

Section: Previous Workmentioning

confidence: 99%

LT-PRPG: Power minimization technique for test-per-scan BIST

Abu-Issa

Quigley

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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This paper presents a new Low Transition PseudoRandom Pattern Generator (LT-PRPG) for test-per-scan Built-In Self-Test (BIST) applications. The proposed LT-PRPG is composed of a LFSR and a 2x1 multiplexer. When used to generate test patterns for test-per-scan BIST, it reduces the number of transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CircuitUnder-Test (CUT) during the test application. Various properties of the proposed LT-PRPG and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity by 36% to 47% with a negligible effect on the fault coverage.Keywords-low power test, built-in self-test, linear feedback shift register, test pattern generator, weighted switching activity.

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Section: Previous Workmentioning

confidence: 99%

LT-PRPG: Power minimization technique for test-per-scan BIST

Abu-Issa

Quigley

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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“…Furthermore, it fails in reducing peak-power consumption since it is independent of clock frequency. Another category of techniques used to reduce the power consumption in scan-based built-in self-tests (BISTs) is by using scan chain-ordering techniques [7]- [13]. These techniques aim to reduce the average-power consumption when scanning in test vectors and scanning out captured responses.…”

Section: Introductionmentioning

confidence: 99%

Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping LFSR and Check-Chain Ordering

Naik¹,

Rao²

2012

IOSRJCE

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In this paper the proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer. When used to generate test patterns for check-based built-in self-tests, it reduces the number of transitions that occur at the check-chain input during check shift operation by 50% when compared to those patterns produced by standard LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR is combined with a check chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (check and capture) in the test cycle or while checking out a response to a sign pattern analyzer. These techniques have a substantial effect on average-and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results bench mark circuits show up to 65% and 55% reductions in average and peak power, respectively.

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Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST

Abu-Issa¹,

Quigley²

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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An efficient algorithm to reduce test power consumption by scan cell and scan vector reordering

Cited by 4 publications

References 10 publications

LT-PRPG: Power minimization technique for test-per-scan BIST

LT-PRPG: Power minimization technique for test-per-scan BIST

Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping LFSR and Check-Chain Ordering

Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST

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