An Efficient Algorithm for VC-1 to H.264 Video Transcoding in Progressive Compression

Lee, J.-B.; Kalva, Hari

doi:10.1109/icme.2006.262548

Cited by 10 publications

(13 citation statements)

References 9 publications

(7 reference statements)

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“…Therefore today we see an increased need for computational power to enable new and emerging applications. As an example, the new video compression standards MPEG-4.10 (also known as H.264) or Microsoft_s VC-1 require computational power that cannot be found in any ordinary PC or workstation to produce high-definition compression in real time [26,34]. However, there is a growing demand for this functionality in different spaces, from video-over-IP to high-definition video conferencing.…”

Section: The Third Big Chipmentioning

confidence: 99%

Finding the Next Computational Model: Experience with the UCSC Kestrel

Hughey

Blas

2007

J Sign Process Syst Sign Image Video Technol

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Architects and industry have been searching for the next durable computational model, the next step beyond the standard CPU. Graphics co-processors, though ubiquitous and powerful, can only be effectively used on a limited range of stream-based applications. The UCSC Kestrel parallel processor is part of a continuum of parallel processing architectures, stretching from the application-specific through the application-specialized to the application-unspecific. Kestrel combines an ALU, multiplier, and local memory, with Systolic Shared Registers for seamless merging of communication and computation, and an innovative condition stack for rapid conditionals. The result has been a readily programmable and efficient co-processor for a wide range of applications, including biological sequence analysis, image processing, and irregular problems. Experience with Kestrel indicates that programmable systolic processing, and its natural combination with the Single InstructionMultiple Data (SIMD) parallel architecture, is the most powerful, flexible, and power-efficient computational model available for a large group of applications. Unlike other approaches that try to displace or replace the standard serial processor, our model recognizes that the expansion in the application landscape and performance requirements simply imply that the most efficient solution is the combination of more than one type of processor. We propose a model in which the CPU and the GPU are complemented by Bthe third big chip,^a massively-parallel SIMD processor.

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Section: The Third Big Chipmentioning

confidence: 99%

Finding the Next Computational Model: Experience with the UCSC Kestrel

Hughey

Blas

2007

J Sign Process Syst Sign Image Video Technol

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“…Algorithms for arbitrary size scaling use DCT matrices of several sizes but in our case we only have H.264 transforms for sizes 4×4 and 8×8, therefore transcoding VC-1 to H.264 can only be done with scaling by a factor of 2 in each dimension. Our approach uses the transcoder described in [5][6][7] but modified to perform down sampling and is described as follows (Fig. 7).…”

Section: Down Samplingmentioning

confidence: 99%

“…We use the transcoder described in [5][6][7] Figure 7 Down sampling an 8×8 block in VC-1 to a 4×4 block in H.264 in the transform domain. …”

Section: Up Samplingmentioning

confidence: 99%

“…Two main approaches are used for transcoding [5]. First, pixel domain transcoding in which the input video is fully decoded followed by an accelerated encoding stage that reuses information gathered during the decoding.…”

Section: Introductionmentioning

confidence: 99%

“…We then analyze the problem of quality enhancement in transcoding VC-1 to H.264 when down/up sampling is used. To transcode Iframes we use the pixel domain transcoder described in [5,6] modified to perform down/up sampling (Fig. 1).…”

Section: Introductionmentioning

confidence: 99%

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Transcoding with Resolution Conversion Using Super-Resolution and Irregular Sampling

Pantoja

Ling

2009

J Sign Process Syst

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In transcoding, quantization and other techniques could result in lower video output quality. To address this problem a novel super-resolution (SR) algorithm based on irregular sampling (IS) is presented in this paper. The highresolution (HR) frame is obtained as an interpolation of one or more previous frames; the resulting interpolated frame has samples non-uniformly spaced in the areas where movement happened. To reconstruct the irregular sampled frame we use a well-known irregular sampling algorithm modified to perform in 2-D space. Moreover, because SR algorithms are in general computationally expensive, we also present a hardware feasibility study. The proposed solution does not target any specific application but we have specifically tested the algorithm in a transcoding environment. In particular, we have applied it to VC-1 to H.264 transcoding and applied down/up sampling. Experimental results show that the proposed algorithm improves video quality significantly.

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