An effective hybrid transactional memory system with strong isolation guarantees

Minh, Chi Cao; Trautmann, Martin; Chung, JaeWoong; McDonald, Austen; Bronson, Nathan; Casper, Jared; Kozyrakis, Christos; Olukotun, Kunle

doi:10.1145/1250662.1250673

Cited by 216 publications

(136 citation statements)

References 29 publications

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“…An important trend is to provide hardware support for TM [50][51][52][53][54][55][56][57][58][59][60][61]. With hardware support, the performance trade-offs change-e.g., the transactional overhead of loads and stores may be virtually eliminated.…”

Section: Related Workmentioning

confidence: 99%

Adaptive locks: Combining transactions and locks for efficient concurrency

Usui

Behrends

Evans

et al. 2010

Journal of Parallel and Distributed Computing

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Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming model and maximizes concurrency. At the same time, transactions can suffer from interference that causes them to often abort, from heavy overheads for memory accesses, and from expressiveness limitations (e.g., for I/O operations). In this paper we propose an adaptive locking technique that dynamically observes whether a critical section would be best executed transactionally or while holding a mutex lock.The critical new elements of our approach include the adaptivity logic and cost-benefit analysis, a low-overhead implementation of statistics collection and adaptive locking in a full C compiler, and an exposition of the effects on the programming model. In experiments with both micro-and macro-benchmarks we found adaptive locks to consistently match or outperform the better of the two component mechanisms (mutexes or transactions). Compared to either mechanism alone, adaptive locks often provide 3-to-10x speedups. Additionally, adaptive locks simplify the programming model by reducing the need for fine-grained locking: with adaptive locks, the programmer can specify coarse-grained locking annotations and often achieve fine-grained locking performance due to the transactional memory mechanisms.

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Section: Related Workmentioning

confidence: 99%

Adaptive locks: Combining transactions and locks for efficient concurrency

Usui

Behrends

Evans

et al. 2010

Journal of Parallel and Distributed Computing

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“…A lock-based STM adds four main overheads when compared with running the same transactions on a native HTM (as in [27]). First, the locking mechanism itself is not necessary in a HTM system.…”

Section: Hybrid-tmmentioning

confidence: 99%

“…Even the simplest, blocking implementations of STM impose a significant slowdown. One approach to improve performance is hardware-accelerated TM (Ha-TM) in which a STM uses new hardware features to perform part of the transaction's work [27,31,34]. An alternative approach is hybrid TM (Hy-TM) [4,17], in which the system supports the coexistence of HW and SW transactions, typically by starting a transaction in HW and re-executing it in SW if it overflows limited resources.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Transactional Memory with Pessimistic Concurrency Control

Vallejo

Sanyal

Harris

et al. 2010

Int J Parallel Prog

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Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being modified. Such implementations can suffer from the "privatization" problem, in which transactional and non-transactional accesses to the same location can lead to inconsistent results.123 376 Int J Parallel Prog (2011) 39:375-396 TM design is proposed to reduce the performance overheads caused by the use of these locks while combining three desirable features: (i) full TM functionality whether or not the architectural support is present; (ii) execution of a single common code path in software or hardware; and, (iii) immunity from the privatization problem. The analysis shows how a Hybrid TM can lose important properties, such as starvation freedom. To overcome this issue, Directory Reservations is presented, a low-cost mechanism improving existent solutions designed for Hardware TM.

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“…and seeks to reduce programming effort, while maintaining or improving execution performance. Support for the TM model on multi-core architectures has been the focus of several recent research efforts, both in hardware [21,25,36,45] and software implementations [10,11,22,23,26,27,44], and also in hybrid implementations [9,33].…”

Section: Introductionmentioning

confidence: 99%

Window-based greedy contention management for transactional memory: theory and practice

Sharma

Busch

2012

Distrib. Comput.

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We consider greedy contention managers for transactional memory for M × N execution windows of transactions with M threads and N transactions per thread. We present, formally analyze, and experimentally evaluate three new randomized greedy contention management algorithms for transaction windows. Assuming that each transaction has duration τ and conflicts with at most C other transactions inside the window, the first algorithm Offline-Greedy produces a schedule of length O(τ ·(C+N ·log(M N ))) with high probability. The offline algorithm depends on knowing the conflict graph which evolves while the execution of the transactions progresses. The second algorithm Online-Greedy produces a schedule of length that is only a logarithmic factor worse than Offline-Greedy, but does not require knowledge of the conflict graph. The third algorithm Adaptive-Greedy is the adaptive version of the previous algorithms which produces a schedule of length asymptotically the same as with online algorithm by adaptively guessing the value of C. All of the algorithms exhibit competitive ratio very close to O(s), where s is the number of shared resources, and at the same time, our algorithms provide new non-trivial tradeoffs for greedy transaction scheduling that parameterize window sizes and transaction conflicts within the execution window. We evaluate these window-based algorithms experimentally using the sorted link list, red-black tree, skip list, and vacation benchmarks. The evaluation results confirm This paper combines and extends preliminary results that appeared in [42,43]. their benefits in practical performance throughput and other metrics such as aborts per commit ratio and execution time overhead, along with the non-trivial provable properties of the algorithms.

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An effective hybrid transactional memory system with strong isolation guarantees

Cited by 216 publications

References 29 publications

Adaptive locks: Combining transactions and locks for efficient concurrency

Adaptive locks: Combining transactions and locks for efficient concurrency

Hybrid Transactional Memory with Pessimistic Concurrency Control

Window-based greedy contention management for transactional memory: theory and practice

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