An EDA tool for implementation of low power and secure crypto-chips

Ghavami, Behnam; Pedram, Hossein; Najibi, Mehrdad

doi:10.1016/j.compeleceng.2008.06.014

Cited by 13 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Section: Dual-vth Asynchronous Circuit Design Frameworkmentioning

confidence: 99%

“…AsyncTool (Ghavami et al , 2009) is an asynchronous synthesis tool developed for automatic synthesis of QDI asynchronous circuits. AsyncTool uses pre-charge logic full-buffer (PCFB) templates (Ghavami et al , 2009) for its predefined templates. Behavioral description will be converted to a netlist of standard-cell elements through several steps of synthesis flow.…”

Section: Dual-vth Asynchronous Circuit Design Frameworkmentioning

confidence: 99%

See 1 more Smart Citation

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

Ghavami

2018

COMPEL

Self Cite

View full text Add to dashboard Cite

Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

show abstract

Section: Dual-vth Asynchronous Circuit Design Frameworkmentioning

confidence: 99%

Section: Dual-vth Asynchronous Circuit Design Frameworkmentioning

confidence: 99%

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

Ghavami

2018

COMPEL

Self Cite

View full text Add to dashboard Cite

show abstract

“…The previous work in [9] presented a finite impulse response (FIR) filter with an asynchronous technique working at 0.3 V, which overcame the timing handling problem with 70% energy savings. However, due to the lack of computer-aided design (CAD) tools for the synthesis and optimization of asynchronous circuits, the implementation of the asynchronous systems faces many design difficulties [10].…”

Section: Introductionmentioning

confidence: 99%

Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics

Rim

Choi

2012

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Subthreshold logic has become an attractive option in energy-constrained applications, where the key metric is energy consumption rather than operating speed or silicon area. However, the performance of circuits operating in the subthreshold region is extremely sensitive to the variations in the process, supply voltage, and temperature (PVT). Generally, circuit designers increase the clock period in order to reduce the timing failures, as well as to ensure the correct operations under all PVT conditions. However, increasing the clock period up to the worst-case critical path delay incurs a significant increase in the active leakage energy. This brief presents an adaptive clock generation scheme for subthreshold logics, wherein a replica module inside measures the variations and helps generate a clock with the correct period. As a result, considerable energy savings is achieved, along with a reduction in the setup time violations. The experimental results obtained with a 0.13-μm CMOS process show that the proposed scheme achieves energy savings of up to 63.8% with the selection of four different clock cycles under a supply voltage of 0.3 V.Index Terms-Active leakage energy, subthreshold logics, ultralow voltage.

show abstract

Application of EDA Technology in the Education of Automatic Control System Design

Wang

2011

Advances in Computer Science, Environment, Ecoinformatics, and Education

View full text Add to dashboard Cite

An EDA tool for implementation of low power and secure crypto-chips

Cited by 13 publications

References 11 publications

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics

Application of EDA Technology in the Education of Automatic Control System Design

Contact Info

Product

Resources

About