2010
DOI: 10.1007/978-3-642-16822-2_16
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An ECDSA Processor for RFID Authentication

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Cited by 34 publications
(28 citation statements)
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“…For ECDSA signature generation, our processor needs 15,387 GEs which outperforms existing solutions in terms of area, power, and speed [13,18,34,35]. Signature verification can be realized using a chip area of 16,005 GEs.…”
Section: Results For Higher-level Protocol Implementationsmentioning
confidence: 99%
“…For ECDSA signature generation, our processor needs 15,387 GEs which outperforms existing solutions in terms of area, power, and speed [13,18,34,35]. Signature verification can be realized using a chip area of 16,005 GEs.…”
Section: Results For Higher-level Protocol Implementationsmentioning
confidence: 99%
“…suggested frequency results in a reasonable performance for RFID applications while reducing power consumption.The paper presents a 192-bit elliptic curve digital signature algorithm process that allows entity and message authentication by digitally signing the challenges from the reader.The proposed architecture enhances the state of art in designing low resource ECDSA-enabled RFID.A tiny microcontroller used to provide protocol stability and re-use of common algorithms [7].…”
Section: Related Work and Contributionsmentioning
confidence: 99%
“…Hence we implement the Schnorr protocol using 192-bit ECC over prime fields which offers higher security compared with 1024-bit RSA. Highly efficient ECC and ECDSA implementations for contrained environments can be found in [28] [29]. However, in this work, we present two new designs which are optimized both for area and timing suited for integration with the standard JTAG.…”
Section: Implementation Of the Ecc Processormentioning
confidence: 99%
“…The area requirement in our designs can be reduced further by making use of a tiny custom microcontroller with an Instruction Set Extension (ISE), as in [28]. Here only the top-level ECDSA commands are managed with a processor.…”
Section: Area Overheadmentioning
confidence: 99%
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