An asynchronous, iterative implementation of the original booth multiplication algorithm

Efthymiou, A.; Suntiamorntut, W.; Garside, Jim; Brackenbury, Linda E. M.

doi:10.1109/async.2004.1299304

Cited by 7 publications

(10 citation statements)

References 4 publications

(9 reference statements)

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“…Finally, C4 indicates that a nonzero multiple is 2. These signals (defined in Table I) are given by (2) and may be efficiently implemented in hardware using the circuits as shown in Fig. 1.…”

Section: Real-time Csd Multiplier Structurementioning

confidence: 99%

“…Moreover, by executing a number of iterations that are data dependent, the energy efficiency can be greatly improved relative to array and parallel multipliers. Here, energy efficiency refers to the energy required per operation, e.g., nano-Joules/op [2]. Therefore, the choice between implementing a parallel or array multiplier as opposed to an iterative multiplier in any given design is generally a trade-off of computational speed against area requirement and energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, the number of iterations required in a multiply directly impacts both the throughput and the energy efficiency of the multiplier. A variety of techniques have been developed to reduce the number of iterations, thereby increasing the efficiency of the shift/add operations [2], [3], [10]; detailed descriptions of several of these are given in Section II below.…”

Section: Introductionmentioning

confidence: 99%

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Iterative Radix-8 Multiplier Structure Based on a Novel Real-time CSD Recoding

Wang

DeBrunner

Havlicek

et al. 2007

2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers

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Real-time implementation of many digital signal processing (DSP) algorithms and multimedia applications is performance limited by the available speed, energy efficiency, and area requirement of multiplication. This is exacerbated in handheld multimedia devices due to the small size and limited battery lifetimes. In our previous work, we introduce a novel canonical signed digit (CSD) iterative multiplier structure in which the conversion from 2's complement to CSD representation is implicitly implemented in real-time. In this work, we further improve the iterative multiplier performance by introducing explicit radix-8 hardware support in which the multiplier is shifted by one octal digit in each iteration as opposed to only one or two bits. Thus, this new structure further reduces the power consumption while simultaneously increasing the computational bandwidth significantly with only a small sacrifice in area consumption. This new design also uses a bypass technique to further reduce the need for devices such as carry save adder (CSA) arrays and adder trees for partial product reduction operations. Therefore, the new structure introduced here greatly improves the multiplier throughput and energy efficiency. Moreover, the number of iterations required to complete a fixed length multiply is data dependent as a result of a novel variable shifting technique; hence there is no energy and time overhead expended for unnecessary iterations as observed in multipliers where the number of iterations is fixed. Our results show that this new iterative structure delivers significant performance improvements with respect to speed, area, and power consumption relative to previous iterative multiplier designs.

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Section: Real-time Csd Multiplier Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Iterative Radix-8 Multiplier Structure Based on a Novel Real-time CSD Recoding

Wang

DeBrunner

Havlicek

et al. 2007

2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers

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“…Along these lines, Efthymious et al [7] proposed an asynchronous multiplier implementation based on the original Booth algorithm [3]. Their design scans the multiplier operand and skips chains of consecutive ones or zeros.…”

Section: A Iterative Multipliersmentioning

confidence: 99%

“…In terms of the multiplier design, the delay variability nature of iterative multipliers makes them a popular choice amongst asynchronous designers [7,12]. An iterative multiplier utilizes a few functional units repeatedly to produce the result.…”

Section: A Asynchronous Multipliers and Floating-point Arithmeticmentioning

confidence: 99%

An Asynchronous Floating-Point Multiplier

Sheikh

Manohar

2012

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems

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Abstract-We present the details of our energy-efficient asynchronous floating-point multiplier (FPM). We discuss design trade-offs of various multiplier implementations. A higher radix array multiplier design with operand-dependent carrypropagation adder and low handshake overhead pipeline design is presented, which yields significant energy savings while preserving the average throughput. Our FPM also includes a hardware implementation of denormal and underflow cases. When compared against a custom synchronous FPM design, our asynchronous FPM consumes 3X less energy per operation while operating at 2.3X higher throughput. To our knowledge, this is the first detailed design of a high-performance asynchronous IEEE-754 compliant double-precision floating-point multiplier.Keywords-Floating point arithmetic; asynchronous logic circuits; very-large-scale integration; pipeline processing I. INTRODUCTION Energy-efficient floating-point computation is important for a wide range of applications. Traditionally, VLSI designers primarily relied on CMOS technology and voltage scaling to reduce power consumption [4]. With the transistor threshold voltage fixed [10], V DD has been scaling very slowly if at all, which means all performance improvements come at an increased energy consumption. Furthermore, process variations in deep sub-micron range have made devices far less robust, which is increasingly making it difficult for synchronous designers to overcome the problems associated with clock skew rates and clock distribution [6]. The findings of a recent in-depth study, to explore and devise ways to further scale supercomputer petaFLOP performance by 1000X, indicate the inadequacy of current design practices and technologies to achieve the desired throughput within a sustainable power budget [1]. This underscores a pressing need for alternate design practices, to reduce energy consumption for floating-point computations while preserving robust behavior in advanced technology nodes.At the other end of the spectrum, embedded systems that have traditionally been considered low performance are demanding higher and higher throughput for the same power budget to support compute-intensive floating-point applications that improve the user experience. Since these applications have to be deployed on portable devices with limited batterylife, it is critical that we develop energy-efficient floatingpoint hardware for these embedded systems, not simply high performance floating-point hardware.The IEEE 754 standard [19] for binary floating-point arithmetic provides a precise specification of floating-point number formats, computation operations, and exceptions and their handling. The combination of a vast range of inputs, special cases, and rounding modes makes the hardware implementation of fully IEEE 754 standard compliant floating-point arithmetic a very challenging task. Ignoring certain aspects of the standard can lead to unexpected consequences in the context of numerical algorithms. Hence, most floating-point hardware is IEEE-comp...

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