Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines
DOI: 10.1109/fpga.1994.315606
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An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

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Cited by 18 publications
(4 citation statements)
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“…The result of the multiplication is 64-bits, but only the most significant 32 bits are sent out. As a result, 3.77 x 10 -11 < e -a _< 0.998051781.…”
Section: 00000000000000000000001mentioning
confidence: 99%
See 2 more Smart Citations
“…The result of the multiplication is 64-bits, but only the most significant 32 bits are sent out. As a result, 3.77 x 10 -11 < e -a _< 0.998051781.…”
Section: 00000000000000000000001mentioning
confidence: 99%
“…Since a is a 28-bit binary number, the value comprising bits 27 to 14 of a represent b, and the value comprising bits 13 to 0 of a represent c. The range of values of b and e -6 are" 00000.000000000 < b < 10111.111111111, (3) or 0 _< b _< 23.9980469, (4) which results in 0.9980519 >_ e -b >_ 3.78 10 -11…”
Section: B Fpga Application Designmentioning
confidence: 99%
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“…Work on compilers targeting commercial FPGAs from abstract algorithms written in imperative software programming languages is emphasized since it is closer to the work described in this paper. Work on mapping methods using software [22] and the Transmogrifier C [23] compilers are one of the first compilation approaches for FPGA-based reconfigurable computing systems. Such approaches have identified important issues on compiling for reconfigurable computing but simple representation models have been used.…”
Section: Related Workmentioning
confidence: 99%