An Artificial Neuron with a Leaky Fin‐Shaped Field‐Effect Transistor for a Highly Scalable Capacitive Neural Network

Han, Joon‐Kyu; Yu, Ji‐Man; Kim, Do Wan; Choi, Yang‐Kyu

doi:10.1002/aisy.202200112

Cited by 3 publications

(5 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These two behaviors verify that the L-FinFET has short-term memory characteristics, which are essential for reservoir operations. In our previous work, the short-term memory property of a SONS-based L-FinFET was found to be caused by the absence of a tunneling oxide barrier, compared to control experiments using another SONOS-based FET with a tunneling oxide barrier . On the other hand, the abovementioned DRAM device can be adopted as a physical reservoir device due to its inherent short-term memory function.…”

Section: Resultsmentioning

confidence: 98%

“…In our previous work, the short-term memory property of a SONS-based L-FinFET was found to be caused by the absence of a tunneling oxide barrier, compared to control experiments using another SONOS-based FET with a tunneling oxide barrier. 19 On the other hand, the abovementioned DRAM device can be adopted as a physical reservoir device due to its inherent short-term memory function. Nonetheless, it is rarely applied in this way owing to the lack of multiple memory states.…”

Section: ■ Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Han

Yun

et al. 2023

ACS Appl. Mater. Interfaces

Self Cite

View full text Add to dashboard Cite

Reservoir computing can greatly reduce the hardware and training costs of recurrent neural networks with temporal data processing. To implement reservoir computing in a hardware form, physical reservoirs transforming sequential inputs into a high-dimensional feature space are necessary. In this work, a physical reservoir with a leaky fin-shaped field-effect transistor (L-FinFET) is demonstrated by the positive use of a short-term memory property arising from the absence of an energy barrier to suppress the tunneling current. Nevertheless, the L-FinFET reservoir does not lose its multiple memory states. The L-FinFET reservoir consumes very low power when encoding temporal inputs because the gate serves as an enabler of the write operation, even in the off-state, due to its physical insulation from the channel. In addition, the small footprint area arising from the scalability of the FinFET due to its multiple-gate structure is advantageous for reducing the chip size. After the experimental proof of 4-bit reservoir operations with 16 states for temporal signal processing, handwritten digits in the Modified National Institute of Standards and Technology dataset are classified by reservoir computing.

show abstract

Section: Resultsmentioning

confidence: 98%

Section: ■ Introductionmentioning

confidence: 99%

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Han

Yun

et al. 2023

ACS Appl. Mater. Interfaces

Self Cite

View full text Add to dashboard Cite

show abstract

“…A less studied element is the memcapacitor 30 . Memcapacitors could theoretically consume lower static power than memristors, see analysis in 31 and other results 32 – 34 . Theoretical work shows that memelements can be described with fractional order integro-differential equations 35 .…”

Section: Introductionmentioning

confidence: 83%

“…Memcapacitors can consume lower static power than memristors, and thus have the potential for building neuromorphic systems orders of magnitude more energy-efficient 31 – 34 . This is because capacitors are electric field based, instead of current based.…”

Section: Discussionmentioning

confidence: 99%

Fractional order memcapacitive neuromorphic elements reproduce and predict neuronal function

Vazquez-Guerrero,

Tuladhar,

Psychalinos

et al. 2024

Sci Rep

View full text Add to dashboard Cite

There is an increasing need to implement neuromorphic systems that are both energetically and computationally efficient. There is also great interest in using electric elements with memory, memelements, that can implement complex neuronal functions intrinsically. A feature not widely incorporated in neuromorphic systems is history-dependent action potential time adaptation which is widely seen in real cells. Previous theoretical work shows that power-law history dependent spike time adaptation, seen in several brain areas and species, can be modeled with fractional order differential equations. Here, we show that fractional order spiking neurons can be implemented using super-capacitors. The super-capacitors have fractional order derivative and memcapacitive properties. We implemented two circuits, a leaky integrate and fire and a Hodgkin–Huxley. Both circuits show power-law spiking time adaptation and optimal coding properties. The spiking dynamics reproduced previously published computer simulations. However, the fractional order Hodgkin–Huxley circuit showed novel dynamics consistent with criticality. We compared the responses of this circuit to recordings from neurons in the weakly-electric fish that have previously been shown to perform fractional order differentiation of their sensory input. The criticality seen in the circuit was confirmed in spontaneous recordings in the live fish. Furthermore, the circuit also predicted long-lasting stimulation that was also corroborated experimentally. Our work shows that fractional order memcapacitors provide intrinsic memory dependence that could allow implementation of computationally efficient neuromorphic devices. Memcapacitors are static elements that consume less energy than the most widely studied memristors, thus allowing the realization of energetically efficient neuromorphic devices.

show abstract

“…New communication elements permit highly interconnected circuits to receive and integrate spikes from a scalable number of silicon neurons (SiNs) [41,42]. It is easy to connect multiple inputs to neuron integrators with capacitive crossbar arrays because they only use dynamic power and a lot less static power than the more common resistive crossbar array [43]. Molybdenum disulfide (MoS2) transistors with a floating gate and two control gates can be used to make individual neurons [44] that have summation and threshold functions built in.…”

Section: Implementing Neural Network Circuitsmentioning

confidence: 99%

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Yeong,

2023

View full text Add to dashboard Cite

Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

show abstract

An Artificial Neuron with a Leaky Fin‐Shaped Field‐Effect Transistor for a Highly Scalable Capacitive Neural Network

Cited by 3 publications

References 28 publications

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Fractional order memcapacitive neuromorphic elements reproduce and predict neuronal function

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Contact Info

Product

Resources

About