An Area Optimized Reconfigurable Encryptor for AES-Rijndael

Abstract

This paper presents a reconfigurable architecture of the Advanced Encryption Standard (AES-Rijndael) cryptosystem. The suggested reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. The work develops a FSMD model based controller which is ideal for such iterative implementation of AES. S-boxes here have been implemented using combinational logic over composite field arithmetic which completely eliminates the need of any internal memory. The design has been implemented on Xilinx Vertex XCV1000 and 0.18µ CMOS technology. The performance of the architecture has been compared with existing results in the literature and has been found to be the most compact implementations of the AES algorithm.

A new fault attack on the advanced encryption standard hardware

“…Two common alternative architectures adopted while implementing the AES in hardware are fully-pipelined and iterative with inner pipe-lining [12], [13]. Certain implementations of AES-Rijndael requires pipelining at all stages (unrolled rounds), due to the requirement of throughput.…”

Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm

“…This 32-bit architecture performs encryption and decryption for various key sizes, but fixed block size (128-bit). The most area optimized reconfigurable AES-Rijndael implementation to date was demonstrated by Monjur et al [3]. This work developed a FSMD model based controller which is ideal for such iterative implementation of AES.…”

“…The advent of composite field GF((2 4 ) 2 ) arithmetic in S-box operation was first noted in the works of Rijmen [4] and Rudra et al [6]. Among the designers who tried to produce an area optimized implementation using composite field arithmetic, the works [3], [7], [8] are of importance. Feldhofer et al [7] implemented 128-bit AES on a grain of sand.…”

“…Over the recent years many FPGA [9], [10], [14], [16], [17], [21] and ASIC [3], [5], [6], [7], [8], [11], [18] implementations for Rijndael has been reported. Most of them have used lookup tables to implement S-Boxes.…”

Differential Fault Analysis of the Advanced Encryption Standard Using a Single Fault

“…The implementation of AES we target is an iterative one, as described in [1]. The literature shows that unrolled or pipelined designs of AES are unpopular because they do not allow a block cipher to operate in Output Feedback Mode (OFB) or Cipher Block Chaining (CBC) mode [17].…”