An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding

Masera, Maurizio; Masera, Guido; Martina, Maurizio

doi:10.1109/tcsvt.2018.2886736

Cited by 16 publications

(4 citation statements)

References 22 publications

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“…The proposed method has reduced rate-distortion losses and achieved significant complexity savings compared to existing implementations. Two families of architectures for the 2D-DCT are designed: folded and full-parallel [9]. The proposed method uses Integer DCT approximation which yields higher mean square error deviations.…”

Section: Existing Modelsmentioning

confidence: 99%

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An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

2023

IJIES

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The Discrete Cosine Transform (DCT) is a basic transform block used in Adaptive Multicore Transform (AMT), which is a core of High Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) standards. AMT uses artificial intelligence technique to decide on the transform output. The suggested One-Dimensional DCT architecture is conceived by 8-point structure Loeffler-DCT technique and synthesized using a floating-point Arithmetic. By preserving the structural regularity as the Loeffler-based design, the optimized floating-point architecture consumes optimum space and delay thereby increasing the precision. The work focuses on obtaining high precision output without compromising on ADP (Area-Delay-Product). Due to the fact that the floating-point multiplier unit is developed using shift-add operations, the results reveal the accomplishment of better resolution output while maintaining Root Mean Square deviation as low as 0.0062. A total of 117 additions, 66 shifts are employed in the suggested architecture. The proposed 1D-DCT is used as a sub-block in developing the architecture of 2D-DCT using only 50% of the 1D-DCT subblocks that is needed for the conventional technique. The 8 X 8 2-D DCT, is computed using only 8 1-D DCT's and additions, instead of using 16 1-D DCT's, as in the traditional row-column method. The model is tested with standard images, which resulted in better PSNR and MSE compared to the standard method. In comparison to the state-of-the-art on DCT, the proposed method obtains a root mean square error that is negligible up to three decimal places resulting in improvement of PSNR by 17%, with a maximum clock frequency of 496MHz has been achieved. The proposed design strikes a balance between trade-off parameters such as area, speed, and precision.

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Section: Existing Modelsmentioning

confidence: 99%

“…𝛽 ρ𝑙 is computed for odd value of n using (9). The quotient 𝑞 𝜌𝑖 is computed as (ρi + (ρ-1)/2)/N, to adjust the sign of 𝛽 ρ𝑙 .…”

Section: D-dct Using N 1d-dctmentioning

confidence: 99%

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

2023

IJIES

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“…In [7], distributed arithmetic techniques [20] are used to implement the multipliers with simple shift and accumulator circuits. In [13], a n-dimensional Reduced Adder Graph (RAG-n) algorithm [21] is used to minimize the number of adders in add-shift-based multiplication circuits.…”

Section: A Proposals Related To the Hevc Standardmentioning

confidence: 99%

“…In [11], the results of the first 1D transform are transposed before they are written into the memory; thus, the 1D transform processors use the transposition memory as a simple memory buffer. In [13], the first 1D processor writes the first transform results row-wise in the transposition buffer, and the second 1D processor reads them column-wise; at the same time, the first 1D processor writes the second transform results column-wise, and so on.…”

Section: A Proposals Related To the Hevc Standardmentioning

confidence: 99%

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

et al. 2020

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Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size. INDEX TERMS FPGA, hardware architecture, multiple transform selection, pipeline, SoPC, versatile video coding. * The architecture proposed in this paper has been implemented and tested in accordance with WD 4. † The number of multiplications required by a direct implementation of a 2D N×N point DCT/DST is N 2 .

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Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding

Nguyen,

Dang,

Bui

et al. 2024

Computational Science and Its Applications – ICCSA 2024 Workshops

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An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding

Cited by 16 publications

References 22 publications

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding

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