An Area-Efficient and Programmable 4 × 25-to-28.9 Gb/s Optical Receiver with DCOC in 0.13 µm SiGe BiCMOS

Abstract

In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic capacitor utilization in the DCOC loop and capacitive emitter degeneration in the variable-gain amplifier (VGA) stage, the chip area is minimized. Fabricated in a 0.13 µm SiGe BiCMOS technology, the receiver achieved a small area of 0.54 mm2 per lane. The measured bit error rate (BER) is 10−12 with input signal varying from 110 μApp to 1150 μApp. The one-lane power dissipation values in the low-power and high-power modes are 84.97 mW and 123.75 mW, respectively.