An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes

Abstract

The quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power. The architecture implements the normalized min-sum algorithm, rearranges the original two-phase message-passing flow, and adopts an efficient quantization method for the second minimum absolute values, an optimized storing scheme for the position indexes and signs, and an elaborate clock gating technique for substantive memories and registers. It is also configurable for any regular and irregular QC-LDPC codes, and can be easily tuned up to different code rates and code word lengths. The chip is fabricated in an SMIC 0.18-m six-metal-layer standard CMOS technology. It attains a throughput of 104.5 Mb/s, and dissipates an average power of 486 mW at 125 MHz, and 15 decoding iterations. The core area is only 9.76 mm 2 . The chip has been applied into the China digital terrestrial/television multimedia broadcasting system. IndexTerms-Digital terrestrial/television multimedia broadcasting (DTMB) system, iterative decoder architecture, min-sum-with-normalization-factor algorithm, quasi-cyclic low-density parity-check (QC-LDPC) codes, VLSI implementation.

Conditional termination check min-sum algorithm for efficient LDPC decoders

“…Therefore, C2V messages are formatted with four components: fsigns, index of min 1, min 1, min 2g. To reduce memory usage of an LDPC decoder, [9] reduced the size of a C2V message by sending the difference of min 1 and min 2, Ámin, instead of min 2, and saved the memory usage by 5.64% with negligible performance loss.…”

“…The number of the CN and VN units in such a decoder ranges from 8 to 128 or more [2,9]. The Ámin values of multiple CN units are added to compute the deltaminima, and its hardware cost is negligible considering that a partly parallel decoder requires multiple CN and VN units.…”

“…In this Letter, a conditional termination check scheduling approach of MSA without SNR estimation is proposed. The proposed scheme is based on the difference of the first two minima from variable to check (V2C) node messages, which was devised in [2,9] to compress check to variable (C2V) node messages to reduce interconnection complexity and memory usage of LDPC decoders.…”

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

“…Since the sequential operation and flexibility between two updates, TPMP algorithm can be rearranged into many modified schedule [6]. To make a tradeoff between decoding performance and hardware complexity, a Modified Min-Sum (MSA) algorithm based on Rearranged Schedule TPMP algorithm (RS-TPMP) [31] is adopted to decode a zM b × zN b Block-LDPC codes and expressed as follows: 1) Initialization:…”

“…However, this novel decoding algorithm is not suitable for unstructured Block-LDPC codes [8] unless a certain amount of performance and throughput are lost. Almost all of the research on LDPC decoder design so far has focused on high throughput, low area and low power consumption, supporting multiple code rates and code lengths, in which specific optimizations are made to improve the decoder performance [9]- [14], [22], [24]- [31]. On the other hand, techniques such as ASIP, NOC have been adopted to implement generic and reconfigurable LDPC decoder [15], [32]- [34].…”