An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

Tang, Song-Nien; Liao, C.-Y.; Chang, Tsin‐Yuan

doi:10.1109/jssc.2012.2187406

Cited by 70 publications

(37 citation statements)

References 24 publications

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“…Each radix-2 stage includes a BF2/IO unit, which performs addition and subtraction of the input for radix-2 execution (BF2 mode) or routes the input and the FIFO data for In/Out delivery (IO mode). The radix-2 k -based pipelined FFT architecture helps to reduce the costs associated with multiplication hardware [13]- [15]. In each set of radix-2 k stages (k = 3 or 4), only an area-efficient constant multiplier is required, and complex multipliers are employed only among the radix-2 k -stage sets.…”

Section: Cfft-based Rfft Computationmentioning

confidence: 99%

“…For FPGA-based designs, we employ the lookup table approach to take advantage of the large number of usable memory devices that can be embedded in an FPGA chip. To reduce table capacity, we apply a dynamic scaling scheme [15] to the RFFT output (a+j*b), wherein data is represented in floating-point form (2 E , where M is the data mantissa and E is the data exponent), as shown in Eq. (1).…”

Section: Memory-based Display Processingmentioning

confidence: 99%

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FDOCT imaging processor for portable OCT systems with high imaging rate

Tang

Hsiang

Huang

et al. 2018

IEICE Electron. Express

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Frequency-domain optical coherence tomography (FDOCT) has been widely applied in medical image inspection. This paper presents an image formation processor capable of performing all FDOCT imaging operations, including DC noise removal, re-sampling, realvalued fast Fourier transform (RFFT), and display processing. A hardware-efficient RFFT unit and memory-based display processing engine make it possible to generate gray-scale display data at high OCT imaging rates. System-level design verification was performed using an FPGA platform and a mobile phone to evaluate the efficacy of the proposed scheme.

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Section: Cfft-based Rfft Computationmentioning

confidence: 99%

Section: Memory-based Display Processingmentioning

confidence: 99%

FDOCT imaging processor for portable OCT systems with high imaging rate

Tang

Hsiang

Huang

et al. 2018

IEICE Electron. Express

Self Cite

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“…, 7. Radix-16 and radix-8 can be replaced by radix-2 4 and radix-2 3 respectively to further reduce the number of complex multiplications [1]. Based on our further investigation of FFT signal flow graph (SFG), we reschedule the FFT signal flow structure, as shown in and butterfly computation mode, which is suitable for parallel processing.…”

Section: Parallel Fft Algorithmmentioning

confidence: 99%

“…Generally, they can be divided into two categories: pipeline architecture and memory-based architecture. Pipeline architectures [1] have the advantage of high throughput, but demand high area cost especially for longsize FFT algorithms. Moreover, dynamic overflow protecting is difficult to be applied on the pipeline architecture, so it needs to extend the width of processing data to prevent overflow.…”

mentioning

confidence: 99%

A scalable, fixed-shuffling, parallel FFT butterfly processing architecture for SDR environment

Chen

Liu

Zhang

2014

IEICE Electron. Express

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This paper presents a programmable and high-efficient application specific instruction-set processor (ASIP) for fast Fourier transformation (FFT) processing based on software defined radio (SDR) methodology. It adopts single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. The proposed ASIP features eight parallel radix-2 butterfly computations with fixed vector data shuffling pattern. In addition, a flexible vector address generation unit is proposed to support innerand inter-group addressing mode. Experiment results show that the proposed FFT ASIP is much more flexible than previous works and outperforms state-of-the-art FFT ASIP architectures in term of energyefficiency.

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“…The MDF scheme is utilized in various applications due to its efficient memory usage, but suffers from arithmetic resource utilization and it is rectified in M 2 DF architecture [9], which utilizes the folding transformation technique for the significant reduction of arithmetic resources.…”

Section: …………………………………………………………………………………………………… Introduction:-mentioning

confidence: 99%

Tunable Mixed Decimation Multipath Delay Feedback for Radix 2k FFT

Bhavani¹,

Raju²

2018

IJAR

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The Decimation Multipath Delay Feedback (M 2 DF) is a technique for the radix 2 k FFT, which eliminates the stand by time of arithmetic modules in computing units. In this paper tunable M 2 DF architecture is proposed. In this, tunable arithmetic units are utilized in place of conventional arithmetic units to overcome the under utilization of arithmetic units in conventional M 2 DF architecture. The results show that, the tunable M 2 DF technique utilizes the lesser number of LUTs and slice registers than the conventional M 2 DF technique. In addition, the proposed technique having advantage of high throughput with reduced delay and area compared with conventional M 2 DF.Copy Right, IJAR, 2018,. All rights reserved. …………………………………………………………………………………………………….... Introduction:-Fast Fourier Transform (FFT) is mostly used algorithm for Discrete Fourier Transform computation in the field of signal processing. The area efficient and high performance FFT implementation throws a challenge on the designers. Hardware designers are putting effort to design effectual architectures for the computation of the FFT to meet required specifications and real-time fulfillment of present applications. Various techniques have proposed over the years to tradeoff the area and performance of the FFT. Pipelined architectures [1] are extensively used because they will achieve more throughputs and small latencies relevant for today's applications to achieve small area and to dissipate less power. The single path delay commutators (SDC) [2] are the most popular technique in the serial input and serial output scenarios. Single path delay feedback (SDF) architecture is proposed to reduce the memory banks in the pipelines [3]. The SDF concept extended to radix 2 to radix 2 k [4][5][6]. The high throughput requirements of communication services encouraged to multipath delay commutators [7] and multipath delay feedback (MDF) [8].The MDF structures are formed using multiple interconnected SDFs. The MDF scheme is utilized in various applications due to its efficient memory usage, but suffers from arithmetic resource utilization and it is rectified in M 2 DF architecture [9], which utilizes the folding transformation technique for the significant reduction of arithmetic resources.In this work, tunable M 2 DF architecture is proposed to further reduce the arithmetic operations in terms of number of LUTs and registers.Construction of M 2 DF Architecture:-Design of parallel radix-2 k FFT processor based on folding transformations to derive the folding matrices of DIF and DIT of SDF structures. The pipelined structure is rescheduled by incorporating DIF blocks into DIT blocks to form

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An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

Cited by 70 publications

References 24 publications

FDOCT imaging processor for portable OCT systems with high imaging rate

FDOCT imaging processor for portable OCT systems with high imaging rate

A scalable, fixed-shuffling, parallel FFT butterfly processing architecture for SDR environment

Tunable Mixed Decimation Multipath Delay Feedback for Radix 2k FFT

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