An architecture for a radix-4 modular pipeline fast Fourier transform

El-Khashab, A.M.; Swartzlander, Earl E.

doi:10.1109/asap.2003.1212861

Cited by 11 publications

(6 citation statements)

References 11 publications

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“…This means (1) can be written in a uniform expression as (10) for all values of Its corresponding CSD representation is 10,1010,1010, 0000,1010, 0010,1010 . (11) where 1 denotes -1.…”

confidence: 99%

“…The authors of [9] proposed pipeline architecture by utilizing digitserial arithmetic and a combined commutator scheme to improve the hardware utilization and decrease the amount of internal buffers. In [10] radix-4 modular pipeline FFT architecture was presented to decompose an N 2 -point FFT into two identical N-point radix-4 pipeline modules with a prerotation multiplier between them. In [11] the authors proposed an improved algorithm for radix-4 and radix-8 FFT to reduce the size of twiddle factor ROMs.…”

Section: Introductionmentioning

confidence: 99%

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A VLSI-oriented FFT algorithm and its pipelined design

Fan¹

2008

2008 9th International Conference on Signal Processing

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This paper presents a novel FFT algorithm based on a multidimensional index mapping method. Twiddle factor multiplications are decomposed in a divide and conquer approach to minimize the number of multipliers and remain the simpleness of the butterfly computation. And canonic signed digit representation is applied to constant multiplications introduced from the decomposition. By exploiting the symmetry of twiddle factors, the algorithm also reduces the memory requirement for twiddle factors. These characteristics make the proposed algorithm suitable for long size FFT VLSI implementation. Based on the algorithm we propose an efficient pipeline FFT architecture and implement a 1024-point FFT processor by 0.18um CMOS technology.

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“…This means (1) can be written in a uniform expression as (10) for all values of Its corresponding CSD representation is 10,1010,1010, 0000,1010, 0010,1010 . (11) where 1 denotes -1.…”

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A VLSI-oriented FFT algorithm and its pipelined design

Fan¹

2008

2008 9th International Conference on Signal Processing

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“…The split systolic approach may be extended to create a Bmodular split systolic^FFT [10] by splitting each of the two 256-point systolic FFTs into pairs of 16-point systolic FFTs as shown on Fig. 15.…”

Section: The Futurementioning

confidence: 99%

Systolic FFT Processors: A Personal Perspective

Swartzlander

2007

J Sign Process Syst Sign Image Video Technol

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This paper provides a personal perspective on developments in the implementation of two systolic fast Fourier transform processors over the last 25 years and identifies some of the lessons learned. This has been a period of tremendous advancements in integrated circuit technology that is demonstrated by the resulting processors. The first processor is the Modular Transform Processor that was developed at TRW in the 1982-1984 time frame using VLSI technology. It is a set of six large circuit boards that computes 4,096-point fast Fourier transforms using 22-bit floating-point arithmetic at sustained data rates of 40 MSPS. The second processor is a single ASIC chip systolic FFT processor developed by the Mayo Foundation in the 2001-2002 time frame that computes 4,096-point FFTs using 16-bit fixed-point arithmetic at sustained data rates of 200 MSPS. Some thoughts on the future directions of systolic FFT processor development are offered. Future systems will compute large transforms (e.g., 16 K-point to 1 M-point) at high data rates (e.g., 500 MSPS to 1 GSPS), will employ more precise arithmetic (e.g., 32-bit single precision IEEE Standard floating-point arithmetic), will consume very low power (e.g., on the order of one watt) and will be realized on a single chip.

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“…El-Khasahab, et al developed the modular pipeline FFT detailed in [18]- [20]. The N-point modular pipeline FFT consists of two N -point FFT modules joined by a specialized center element.…”

Section: The Modular Pipelinementioning

confidence: 99%

“…Further, the MDC pipeline FFT utilizes (r+1)N/2 -r delay elements, and (r-1) (log r N -1) real multipliers and roughly 2(r-1) (log r N -1) adders. Table 14 summarizes the hardware and timing complexities for FFT pipeline architectures discussed in references [18], [20]. The table also illustrates the complexities for the switch based architecture (shown in the last row of the table.)…”

Section: Comparison With Other Fft Pipelinesmentioning

confidence: 99%

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

Mohd¹,

Swartzlander

Aziz³

2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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Abstract. This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme that avoids memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT implementation are presented. The pipeline consists of log 2 N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log 2 N. The pipeline algorithm is configurable to any M > 1.

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An architecture for a radix-4 modular pipeline fast Fourier transform

Cited by 11 publications

References 11 publications

A VLSI-oriented FFT algorithm and its pipelined design

A VLSI-oriented FFT algorithm and its pipelined design

Systolic FFT Processors: A Personal Perspective

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

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