An approach to the approximation problem for nonrecursive digital filters

Rabiner, L. R.; Gold, B.; McGonegal, C. A.

doi:10.1109/tau.1970.1162092

Cited by 152 publications

(36 citation statements)

References 10 publications

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“…Various optimization techniques have been proposed by Gold & Jordan [15], Rabiner et al [16], [17], Herrmann & Schuessler [18] and Herrmann [19] which, along with the classical window design methods reported by Kaiser [20] and Helms [21] provide the user with several possibilities for approximating filters with arbitrary frequency-response characteristics. [19] reported a third technique for designing FIR filters which solves a system of nonlinear equations to generate a filter with an equiripple approximation error.…”

Section: Literature Review On Fir Filters and Their Implementationmentioning

confidence: 99%

FPGA Implementation of Higher Order FIR Filter

Singh¹,

Prakash

2017

IJECE

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it's the maximum operating frequency. Keyword:Fir filter FPGA Higher order fir filter Xilinx

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Section: Literature Review On Fir Filters and Their Implementationmentioning

confidence: 99%

FPGA Implementation of Higher Order FIR Filter

Singh¹,

Prakash

2017

IJECE

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“…The frequency sampling approach is a well-known discrete design technique for obtaining FIR filters [10], [11]. Basically, this technique consists of finding the impulse response coefficients p [n] from a desired frequency response specified at a set of equally spaced frequencies; i.e.,…”

Section: Frequency Sampling Techniquementioning

confidence: 99%

“…To address these issues, this paper deals with the design and implementation of these filters using the frequency sampling approach [10], [11]. In the proposed technique, the coefficients are obtained by means of a procedure which only consists of optimizing the values of the samples in the transition band.…”

Section: Introductionmentioning

confidence: 99%

Polyphase FIR Networks Based on Frequency Sampling for Multirate DSP Applications

Cruz–Roldán

Campo

Godino-Llorente

et al. 2010

Circuits Syst Signal Process

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It is well known that the frequency sampling approach to the design of Finite Impulse Response digital filters allows recursive implementations which are computationally efficient when most of the frequency samples are integers, powers of 2 or nulls. The design and implementation of decimation (or interpolation) filters using this approach is studied herein. Firstly, a procedure is described which optimizes the tradeoff between the stopband energy and the deviation of the passband from the ideal filter.The search space is limited to a small number of samples (in the transition band), imposing the condition that the resulting filter have a large number of zeroes in the stopband. Secondly, three different structures to implement the decimation (or interpolation) filter are proposed. The implementation complexity, i.e. the number of multiplications and additions per input sample, are derived for each structure. The results shown that, without taking into account finite word-length effects, the most efficient implementation depends on the filter length to decimation (or interpolation) ratio.

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“…Filter 3 of Table 3.2 was the first to be designed [36] These degradations are optimistic, mainly due to the linear phase of filter 3, as we shall see when exploring nonlinear-r>hast-filters.…”

Section: Linear-phase Fir Filtermentioning

confidence: 99%

Simulation of a Narrow Bandpass-Limited Satellite Channel

White¹

1976

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The effects of a bandpass-limiting satellite channel, such as a B=25-kHz hard-limiting FLEETSAT channel, on several modulation techniques were simulatedThe modulations included BPSK and various forms of QPSK, including offset QPSK and continuous-phase minimum frequency shift keying (MSK). Coherent matched-filter receivers and both uplink and downlink noise were assumed.For a bit error probability of 0.005 and a SNR loss of less than 1 dB caused by the nonlinearity in the FLEETSAT case, the maximum standard data rate R was 19.2 kbps for BPSK but 32 kbps for offset QPSK, MSK and QPSK.Rates of 24 kbps for BPSK and 48 kbps for offset QPSK and MSK were attainable at this same reliability with a SNR degradation of about 4 dB and 2.5 dB, respectively. Larger degradations are expected at lower error rates.

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An approach to the approximation problem for nonrecursive digital filters

Cited by 152 publications

References 10 publications

FPGA Implementation of Higher Order FIR Filter

FPGA Implementation of Higher Order FIR Filter

Polyphase FIR Networks Based on Frequency Sampling for Multirate DSP Applications

Simulation of a Narrow Bandpass-Limited Satellite Channel

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