An approach to parallel architecture modelling (abstract only)

Abstract

Traditionally, two kinds of models -analytical and &screte-event simulator -have bean used for functional modeling of multiplemicroprocessor architectures ( 1.2). Given the complexity of design emanating from interactions among various components of such architectures -both hardware and software -useful models of such systems are very difficult to build.Analytical models that are used for modeling such architectures are mostly queue networks (3). When such queue networks are used for system modeling, often product-form solutions are not easy to obtain; in such cases, approximate method in the form of hierarchical decomposition or operational analysis (4.5) is adopted to arrive at a particular solution. The results obtained from such analysis may not give the desired degree of accuracy in all such cases.Discrete-event simulation technique can be employed to investigate design alternatives at various stages of design. As such, the degree of detail in a typical such simulator varies -simulation can be performed at behavioural, instruction or at hardwaredescription level. For a typically involved simulator construction however, often the cost and the complexity of simulator design approach! that of the system to be modeled.Further, run-time resource requirement, provisions for static and dynamic reconfiguration and flexibility for experimentation at different levels provide acklitional constraints for such simulator design. An incremental design methdology based on a modified accessgrgh technique (6,7) could be the most ideal approach for such a reconfigurable simulator design (8).The basic components of an access-graph as considered in the present work, are of three types: Process, Monitor, and nodal micro. A process can send or retrieve data from a nodal micro or monitor. Also two processes can communicate with each other through monitors only. Mutual exclusion in monitors has been enforced to ensure that only one process can get access to a monitor at any instant of time. For avoiding deadlock and other undesirable situations, provisions also exist to continue or suspend a process. Starting with a simple source-to-destinationmessage transfer schemethe software components of the simulator are derived in an incrementalfashion usith the help of such acess-graphs through several iterations.The basic structure of the reconfigurable sirnulator consists of two main parts: resource management and message communication FIGURE 1So. to siart with, an access-graph for a message transfer from a single source to a single destination micro (figure 1) node should contain a source process, a communication process and a destination process. Resource management involves only two buffers i 1 an input buffer, to which the source PIDLYSS transfers data frorn the source ncdeand from which the communicator process consume1 s data and ii) an output buffer to which the communicator process transfers data and from which, the data is consumed by the destination process.In the next stage of decomposition, multiple source and destination proce...