An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA

Novickis, Rihards; Justs, Daniels Jānis; Ozols, Kaspars; Greitāns, Modris

doi:10.3390/electronics9122193

Cited by 28 publications

(22 citation statements)

References 27 publications

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“…For further investigations on accuracy loss, fault model of the FPGA with voltage scaling can be extracted to study behavior of the larger models at reduced voltages. The RTL of this model was generated using tools provided in [27].…”

Section: Experiments and Resultsmentioning

confidence: 99%

“…Likewise, at the output an accumulator together with a comparator verifies the integrity from ABFT checksums, and the results are sent to the control processor. The tool chain [27] was modified to automatically generate the necessary RTL code to integrate ABFT into the neural model computations. In addition to network output, the results of the checksum inspection blocks are routed back to the processor to report possible detections during the inference phase as single value output through AXI interfaces [25].…”

Section: B Error Detection Through Abftmentioning

confidence: 99%

See 1 more Smart Citation

Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques

Safarpour¹,

Deng²,

Massingham³

et al. 2021

Preprint

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Operating at reduced voltages offers substantial energy efficiency improvement but at the expense of increasing the probability of computational errors due to hardware faults. In this context, we targeted Deep Neural Networks (DNN) as emerging energy hungry building blocks in embedded applications. Without an error feedback mechanism, blind voltage down-scaling will result in degraded accuracy or total system failure. To enable safe voltage down-scaling, in this paper two solutions based on Self-Supervised Learning (SSL) and Algorithm Based Fault Tolerance (ABFT) were developed. A DNN model trained on MNIST data-set was deployed on a Field Programmable Gate Array (FPGA) that operated at reduced voltages and employed the proposed schemes. The SSL approach provides extremely low-overhead (≈0.2%) fault detection at the cost of lower error coverage and extra training, while ABFT incurs less than 8%overheads at run-time with close to 100% error detection rate. By using the solutions, substantial energy savings, i.e., up to 40.3%,without compromising the accuracy of the model was achieved

show abstract

Section: Experiments and Resultsmentioning

confidence: 99%

Section: B Error Detection Through Abftmentioning

confidence: 99%

Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques

Safarpour¹,

Deng²,

Massingham³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Firmware was written for the ARM processor in the SoC to control the FPGA acting as a neural accelerator. The processor feeds the network with input vectors and fetches the output via AXI ports [27]. For further investigations on accuracy loss, fault model of the FPGA with voltage scaling can be extracted to study behavior of the larger models at reduced voltages.…”

Section: Experiments and Resultsmentioning

confidence: 99%

Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques

Safarpour¹,

Deng²,

Massingham³

et al. 2021

Preprint

View full text Add to dashboard Cite

This paper presents simple techniques to significantly reduced energy consumption of DNNs: Operating at reduced voltages offers substantial energy efficiency improvement but at the expense of increasing the probability of computational errors due to hardware faults. In this context, we targeted Deep Neural Networks (DNN) as emerging energy hungry building blocks in embedded applications. Without an error feedback mechanism, blind voltage down-scaling will result in degraded accuracy or total system failure. To enable safe voltage down-scaling, in this paper two solutions based on Self-Supervised Learning (SSL) and Algorithm Based Fault Tolerance (ABFT) were developed. A DNN model trained on MNIST data-set was deployed on a Field Programmable Gate Array (FPGA) that operated at reduced voltages and employed the proposed schemes. The SSL approach provides extremely low-overhead (≈0.2%) fault detection at the cost of lower error coverage and extra training, while ABFT incurs less than 8%overheads at run-time with close to 100% error detection rate. By using the solutions, substantial energy savings, i.e., up to 40.3%,without compromising the accuracy of the model was achieved

show abstract

“…3. Furthermore, a Fully Connected Neural Network (FC-NN) [17] with ABFT in matrix multiplications in the largest layers was synthesized on the FPGA. The checksum augmentation of the inputs and the inspection of the results were both done by circuit logic on-the-fly.…”

Section: Experimentationmentioning

confidence: 99%

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

Safarpour¹

2021

Preprint

View full text Add to dashboard Cite

show abstract

An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA

Cited by 28 publications

References 27 publications

Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques

Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques

Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection Techniques

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

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