An Approach for Compiler Optimization to Exploit Instruction Level Parallelism

Kumar, R.; Singh, Pradeep Kumar

doi:10.1007/978-3-319-07350-7_56

Cited by 6 publications

(2 citation statements)

References 9 publications

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“…With that said, the most recent insights suggest that conventional compilers and optimisers fail to produce optimal code [71]. In addition, a more recent focus on the GNU GCC compiler collection has shown that the GNU GCC release used within a build toolchain can produce significantly different performance [72].…”

Section: Performance Regressionmentioning

confidence: 99%

Accidental Choices—How JVM Choice and Associated Build Tools Affect Interpreter Performance

2022

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Considering the large number of optimisation techniques that have been integrated into the design of the Java Virtual Machine (JVM) over the last three decades, the Java interpreter continues to persist as a significant bottleneck in the performance of bytecode execution. This paper examines the relationship between Java Runtime Environment (JRE) performance concerning the interpreted execution of Java bytecode and the effect modern compiler selection and integration within the JRE build toolchain has on that performance. We undertook this evaluation relative to a contemporary benchmark suite of application workloads, the Renaissance Benchmark Suite. Our results show that the choice of GNU GCC compiler version used within the JRE build toolchain statistically significantly affects runtime performance. More importantly, not all OpenJDK releases and JRE JVM interpreters are equal. Our results show that OpenJDK JVM interpreter performance is associated with benchmark workload. In addition, in some cases, rolling back to an earlier OpenJDK version and using a more recent GNU GCC compiler within the build toolchain of the JRE can significantly positively impact JRE performance.

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Section: Performance Regressionmentioning

confidence: 99%

Accidental Choices—How JVM Choice and Associated Build Tools Affect Interpreter Performance

2022

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“…The LLVM and trimaran compiler infrastructure use SSA form for all scalar register values in their primary code representation. Some researchers presented steps to convert the intermediate representation in to SSA form [20]. SSA form is optimal and has no unnecessary terms.…”

Section: Related Workmentioning

confidence: 99%

Comparison of Instruction Scheduling and Register Allocation for Mips and HPL-Pd Architecture for Exploitation of Instruction Level Parallelism

Kumar¹

2018

Eng. herit. j.

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The integrated approaches for instruction scheduling and register allocation have been promising area of research for code generation and compiler optimization. In this paper we have proposed an integrated algorithm for instruction scheduling and register allocation and implemented it for compiler optimization in machine description in trimaran infrastructure for exploitation of Instruction level parallelism. Our implementation in trimaran infrastructure shows that our scheduler reduces the number of active live ranges dealt with linear scan allocator. As a result only few spills were needed and the quality of the code generated was improved. For our experiments we used 20 benchmarks available with trimaran infrastructure for HPL-PD architecture. We compare some of these results with results obtained by Haijing Tang et al (2013) performed by LLVM compiler on MIPS architecture. For our experimental work we added machine description (MDES) targeted to HL-PD architecture. The implemented algorithm is based on subgraph isomorphism. The input program is represented in the form of directed acyclic graph (DAG). The vertices of the DAG represent the instructions, input and output operands of the program, while the edges represent dependencies among the instructions.

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An Efficient Machine Learning Approach for Detecting Malwares in IoT Environment

Kumar,

Anand,

Singh

et al. 2023

2023 3rd International Conference on Technological Advancements in Computational Sciences (ICTACS)

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An Approach for Compiler Optimization to Exploit Instruction Level Parallelism

Cited by 6 publications

References 9 publications

Accidental Choices—How JVM Choice and Associated Build Tools Affect Interpreter Performance

Accidental Choices—How JVM Choice and Associated Build Tools Affect Interpreter Performance

Comparison of Instruction Scheduling and Register Allocation for Mips and HPL-Pd Architecture for Exploitation of Instruction Level Parallelism

An Efficient Machine Learning Approach for Detecting Malwares in IoT Environment

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