An application specific instruction set processor (ASIP) for the niederreiter cryptosystem

Hu, Jingwei; Dai, Wangchen; Liu, Yao; Cheung, Ray C. C.

doi:10.1109/isdfs.2018.8355364

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…However, the reference implementation [27] for the BIG-N part of the schemes is not protected against the attack. Furthermore, the other published reference implementations [10] and [11] of the BIG-N cryptosystem use constant weight encoders and decoders whose standard implementation is also vulnerable. Thus, although it may not be very difficult to defend against, apparently all current implementations and applications of the BIG-N cryptosystem are vulnerable to the BIG-N fault attack.…”

Section: Introductionmentioning

confidence: 99%

A fault attack on the Niederreiter cryptosystem using binary irreducible Goppa codes

Danner¹,

Kreuzer²

2020

Journal of Groups, Complexity, Cryptology

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A fault injection framework for the decryption algorithm of the Niederreiter public-key cryptosystem using binary irreducible Goppa codes and classical decoding techniques is described. In particular, we obtain low-degree polynomial equations in parts of the secret key. For the resulting system of polynomial equations, we present an efficient solving strategy and show how to extend certain solutions to alternative secret keys. We also provide estimates for the expected number of required fault injections, apply the framework to state-of-the-art security levels, and propose countermeasures against this type of fault attack. Comment: 20 pages

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Section: Introductionmentioning

confidence: 99%

A fault attack on the Niederreiter cryptosystem using binary irreducible Goppa codes

Danner¹,

Kreuzer²

2020

Journal of Groups, Complexity, Cryptology

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“…In 2018, Hu et al presented an ASIP design implemented on an FPGA, which supports Niederreiter encryption as well as decryption. This architecture is furthermore capable of generating signatures using the Niederreiter cryptosystem[HDYC18]. Furthermore, an FPGA implementation of the complete Niederreiter system providing long-term security with a security level of 266 bit is given in[WSN17] and[WSN18].…”

mentioning

confidence: 99%

Efficient ASIC Architecture for Low Latency Classic McEliece Decoding

Fallnich,

Lanius,

Zhang

et al. 2024

TCHES

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Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available “quantum-resistant” systems, the Classic McEliece key encapsulation mechanism (KEM) is positioned as a conservative choice with strong security guarantees. Building upon the code-based Niederreiter cryptosystem, this KEM enables high performance encapsulation and decapsulation and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Classic McEliece operations. Therefore, the present work targets the design, implementation and optimization of a tailored ASIC architecture for low latency Classic McEliece decoding. An efficient ASIC design is proposed, which was implemented and manufactured in a 22 nm FDSOI CMOS technology node. We also introduce a novel inversionless architecture for the computation of error-locator polynomials as well as a systolic array for combined syndrome computation and polynomial evaluation. With these approaches, the associated optimized architecture improves the latency of computing error-locator polynomials by 47% and the overall decoding latency by 27% compared to a state-of-the-art reference, while requiring only 25% of the area.

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Post-Quantum Cryptosystem of Niederreiter, Algorithm and Encryption Scheme: Modification and Optimization

Sharifov

Kiyashova

Belchikova

et al. 2021

XIV International Scientific Conference “INTERAGROMASH 2021"

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An application specific instruction set processor (ASIP) for the niederreiter cryptosystem

Cited by 3 publications

References 14 publications

A fault attack on the Niederreiter cryptosystem using binary irreducible Goppa codes

A fault attack on the Niederreiter cryptosystem using binary irreducible Goppa codes

Efficient ASIC Architecture for Low Latency Classic McEliece Decoding

Post-Quantum Cryptosystem of Niederreiter, Algorithm and Encryption Scheme: Modification and Optimization

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