An application of functional decomposition in ROM-based FSM implementation in FPGA devices

Rawski, Mariusz; Selvaraj, Henry; Łuba, T.

doi:10.1016/j.sysarc.2004.07.004

Cited by 70 publications

(43 citation statements)

References 10 publications

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“…The set Π A includes I 0 = 5 elements. Using (12), it can be found that R B = 3. Using (3), it can be found that G + L 2 + R B = 7 and, therefore, G + L 1 = 4.…”

Section: Main Idea Of Proposed Methodsmentioning

confidence: 99%

Hardware reduction for RAM-based Moore FSMs

Kołopieńczyk

Barkalov

Titarenko

2014

2014 7th International Conference on Human System Interactions (HSI)

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“…The set Π A includes I 0 = 5 elements. Using (12), it can be found that R B = 3. Using (3), it can be found that G + L 2 + R B = 7 and, therefore, G + L 1 = 4.…”

Section: Main Idea Of Proposed Methodsmentioning

confidence: 99%

Hardware reduction for RAM-based Moore FSMs

Kołopieńczyk

Barkalov

Titarenko

2014

2014 7th International Conference on Human System Interactions (HSI)

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“…If we carefully perform a decomposition of logical structure of protocol, then the FSM state diagram can be easily obtained from the state diagram of the protocol. Input and output functions may be implemented using ROM as demonstrated in [15]. In [16] it is shown that it is possible to combine logic cells and ROM for the realization of the FSM's in order to save resources on the the FPGA unit.…”

Section: F Fsmmentioning

confidence: 99%

Challenges in the design of the MAC protocols for wireless sensor networks using VHDL

Kaljić

Aksamovic

2014

2014 X International Symposium on Telecommunications (BIHTEL)

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In the design of MAC protocols for wireless sensor networks (WSN) it is necessary to fulfill some requirements such as low energy consumption, scalability, simplicity, etc. These requirements are not easy to fulfill from the viewpoint of implementation on FPGA or ASIC technologies. Therefore, in this paper we identify some challenges encountered during the design of MAC protocol for WSN. For some of these challenges, potential solutions are discussed. To illustrate the proposed solutions S-MAC protocol is chosen. VHDL design of the S-MAC protocols is experimentally verified on the Altera EP2C5 FPGA development system.

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“…It is important to find a successful solution for this problem, because it has a direct influence on the quality and cost of digital devices at the design process. It has been shown in [8,18] that a considerable number of papers have been already published on this topic and it is still interesting for the research [21,16,28,6,14,23,19]. The motivation is reducing the complexity of the problem by divide and conquer approach to find an appropriate set of sub-circuits.…”

Section: Introductionmentioning

confidence: 99%

“…The motivation is reducing the complexity of the problem by divide and conquer approach to find an appropriate set of sub-circuits. Efficiency and usefulness of functional decomposition have been demonstrated in theoretical papers [2,9,16,23]. It can be applied in many fields of modern engineering and science, such as combinational and sequential logic synthesis for VLSI systems, machine learning, decision systems, databases, data mining, etc.…”

Section: Introductionmentioning

confidence: 99%

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An input variable partitioning algorithm for functional decomposition of a system of Boolean functions based on the tabular method

Afshord

Pottosin

Arasteh

2015

Discrete Applied Mathematics

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a b s t r a c tFunctional decomposition is a fundamental method for the optimization of multi-level logic circuits by breaking down a complex circuit into smaller and hopefully simpler subcircuits. The problem of searching for an appropriate partition of input variables is the first step in the decomposition process, and it is a challenging task in the logic synthesis. The serial, two-block disjoint decomposition of a system of completely specified Boolean functions is investigated. An input variable partitioning algorithm is proposed, which is used for functional decomposition along with a tabular method. It is based on using the ternary matrix cover approach. A method for constructing the cover map that has the structure of the Karnaugh map is also presented. It is used in a step of the tabular method during the decomposition. There is a chance in a decomposable system, to choose such a solution of the task to reduce the circuit size exponentially. The paper emphasizes on obtaining the best possible partition in an efficient manner. A set of experiments has been carried out on the generated systems of Boolean functions and standard benchmarks. The results confirm the efficiency and effectiveness of the suggested algorithm along with the ternary matrix cover approach. The obtained solutions are optimal in the most cases, according to a certain criterion.

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An application of functional decomposition in ROM-based FSM implementation in FPGA devices

Cited by 70 publications

References 10 publications

Hardware reduction for RAM-based Moore FSMs

Hardware reduction for RAM-based Moore FSMs

Challenges in the design of the MAC protocols for wireless sensor networks using VHDL

An input variable partitioning algorithm for functional decomposition of a system of Boolean functions based on the tabular method

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