An APL Compiler for a Vector Processor

Budd, Timothy A.

doi:10.1145/579.357248

Cited by 39 publications

(17 citation statements)

References 15 publications

(15 reference statements)

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“…ELP [75] is more than two decades old, and even before that compiling e.g. APL for vector processors was considered [76]. However, rather than writing all code in a new language, it is also quite common to generate code from some other specification.…”

Section: Our Solution Uses a Domain Specific Language (Dsl) Called Ftmentioning

confidence: 99%

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Sohl

2015

Linköping Studies in Science and Technology. Dissertations

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Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced.Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs.Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow.More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain?Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance with power efficiency and silicon cost that is comparable to ASICs.The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously.iii iv One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software.Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed.This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to ge...

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Section: Our Solution Uses a Domain Specific Language (Dsl) Called Ftmentioning

confidence: 99%

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Sohl

2015

Linköping Studies in Science and Technology. Dissertations

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“…This reduces locality of reference and thus cache performance. The key innovation in efficient array language compiler development was Budd's [13] principle to create a single loop nest for each array assignment and to create temporaries as scalar results. This principle was subsequently rediscovered by other implementers of data parallel languages or sub-languages [14].…”

Section: Previous Related Workmentioning

confidence: 99%

Compiling Vector Pascal to the XeonPhi

Chimeh

Cockshott

Oehler

et al. 2015

Concurrency and Computation

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SUMMARYIntel's Xeon Phi is a highly parallel x86 architecture chip made by Intel. It has a number of novel features which make it a particularly challenging target for the compiler writer. This paper describes the techniques used to port the Glasgow Vector Pascal Compiler (VPC) to this architecture and assess its performance by comparisons of the Xeon Phi with 3 other machines running the same algorithms. Copyright c 0000 John Wiley & Sons, Ltd. Nvidia GPU CONTEXTThis work was done as part of the EU funded CLOPEMA project whose aim is to develop a cloth folding robot using real time stereo vision. At the start of the project we used a Java legacy software package, C3D [1] that is capable of performing the necessary ranging calculations. When processing the robot's modern high resolution images it was prohibitively slow for real time applications, taking about 20 minutes to process a single pair of images.To improve performance, a new Parallel Pyramid Matcher (PPM) was written in Vector Pascal [2] † , using the legacy software as design basis. The new PPM allowed the use of both SIMD and multi-core parallelism [3]. It performs about 20 times faster on commodity PC chips such as the Intel Sandybridge, than the legacy software. With the forthcoming release of the Xeon Phi it was anticipated to be able to obtain further acceleration running the same PPM code on the Xeon Phi. Hence, taking advantage of more cores and wider SIMD registers, whilst relying on the automatic parallelisation feature of the language. The key step in this would be to modify the compiler to produce Xeon Phi code. However, the Xeon Phi turned out to be considerably more complex compared to previous Intel platforms. Porting of the Glasgow Vector Pascal compiler became an entirely new challenge, and required a different porting approach than previous architectures. PREVIOUS RELATED WORKVector Pascal [4,2] is an array language and as such shares features from other array languages such as APL [5], ZPL [6,7,8] Assignment C [11,12]. The original APL and its descendent J were interpretive languages in which each application of a function to array arguments produced an array result. Whilst it is possible to naively generate a compiler that uses the same approach it is considered inefficient as it leads to the formation of an unnecessary number of array temporaries. This reduces locality of reference and thus cache performance. The key innovation in efficient array language compiler development was Budd's [13] principle to create a single loop nest for each array assignment and to create temporaries as scalar results. This principle was subsequently rediscovered by other implementers of data parallel languages or sub-languages [14]. It has been used in the Saarbrucken [15] Note that the # notation is not supported. Instead index sets are usually elided, provided that the corresponding positions in the arrays are intended. If offsets are intended the index sets can now be explicitly referred to using the predeclared array of index sets iota. iota[0] ...

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“…Considerable research has gone into optimizing arrays in languages such as HPF [30], APL [15], and many others. Our compiler differs in that it applies domain-specific knowledge of linear algebra to handle a wide range of matrix storage formats.…”

Section: Background and Related Workmentioning

confidence: 99%

Automating the generation of composed linear algebra kernels

Belter

Jessup

Karlin

et al. 2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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Memory bandwidth limits the performance of important kernels in many scientific applications. Such applications often use sequences of Basic Linear Algebra Subprograms (BLAS), and highly efficient implementations of those routines enable scientists to achieve high performance at little cost. However, tuning the BLAS in isolation misses opportunities for memory optimization that result from composing multiple subprograms. Because it is not practical to create a library of all BLAS combinations, we have developed a domain-specific compiler that generates them on demand. In this paper, we describe a novel algorithm for compiling linear algebra kernels and searching for the best combination of optimization choices. We also present a new hybrid analytic/empirical method for quickly evaluating the profitability of each optimization. We report experimental results showing speedups of up to 130% relative to the GotoBLAS on an AMD Opteron and up to 137% relative to MKL on an Intel Core 2.

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An APL Compiler for a Vector Processor

Cited by 39 publications

References 15 publications

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Compiling Vector Pascal to the XeonPhi

Automating the generation of composed linear algebra kernels

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