An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

“…[8][9][10][11][12][13] Recently, the Re-S/D SOI MOSFETs have been analyzed in great detail. [8][9][10][11][12][13] Considering the variability problem of threshold voltage owing to the random dopant fluctuation in the doped channel, the back-gate bias is one of the unique features of devices for the ultimate tuning of threshold voltage even after the device has been fabricated. 14,15 The effects of back-gate bias voltage on the threshold voltage of FD SOI MOSFETs have been studied in detail.…”

Improved performance of nanoscale junctionless transistor based on gate engineering approach

“…At the same time, dual-material gate (DMG) devices have been theoretically studied [9][10][11][12][13][14][15][16] and fabricated [17][18][19]. Gate engineering technique such as dual metal gate (DMG) MOSFET has been firstly proposed in which the structure has two gates with different work functions [20].…”

Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs

“…Furthermore, the large series resistance problem of the UTB SOI MOSFETs, which is due to ultrathin body and curbs the current drive capability, has also been resolved by recessing source and drain in the BOX [10,11]. Moreover, better current carrier transportation and reduced hot-carrier effects (HCEs) have also been achieved by redistributing the electric field in the body region with the dual-metal-gate structure [12][13][14].…”

“…Thus, in spite of having an ultra-thin body, a SOI MOSFET with recessed-source/drain (Re-S/D) structure delivers high drain current compared to the conventional SOI MOSFETs. The drain current drive capability of Re-S/D SOI MOSFETs could be further improved if the dual-metal-gate (DMG) structure is adopted in place of the conventional single metal gate [14,25,26]. The DMG structure causes the redistribution in the electric field in the channel region which results in the improved carrier transport in the channel.…”

“…The DMG structure causes the redistribution in the electric field in the channel region which results in the improved carrier transport in the channel. We have shown in our previous work that the subthreshold characteristics of Re-S/D SOI MOSFETs deteriorate due to electrostatic coupling between source/drain and the back channel of the device; however, this degradation in characteristics could be managed up to the acceptable level by choosing the device parameters judiciously [14,25,26]. Thus, a high ON and OFF current ratio could be set for the device if device parameters are selected properly, which may be very attractive for digital circuit design.…”