An Analytical MOS Device Model With Mismatch and Temperature Variation for Subthreshold Circuits

Benjamin, Ben Varkey; Smith, Richelle L.; Boahen, Kwabena

doi:10.1109/tcsii.2023.3234009

Cited by 3 publications

(1 citation statement)

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“…Integrated circuit technology, engaged in a race to reduce the size of chips and circuits, cannot ensure the strict identity of the parameters on the same chip or on different chips. Thus appears the so-called “mismatch”—[ 22 , 23 , 24 , 25 ], whose size is a criterion for the performance of the chips. It is all the more important as the circuit works with lower currents.…”

Section: Introductionmentioning

confidence: 99%

Decision Levels and Resolution for Low-Power Winner-Take-All Circuit

Costea

2023

Sensors

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Sensors in many applications must select the largest element in a sequence of currents. This can be performed in an analog way by the Winner-Take-All (WTA) circuit. This paper considers the classic version of the WTA Lazzaro circuit, working with MOS devices in a subthreshold regime. Since the separation of the gainer by analytically computable “decision levels” has recently been introduced, this paper aims to numerically verify and discuss these levels and their dependence on circuit and device parameters. For VT, the threshold voltage of MOS devices, which is primarily responsible for differences between components (mismatch), its relationship with the output voltages is theoretically demonstrated and numerically checked.

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