An Analytical Model of Drain Current in a Nanoscale Circular Gate TFET

Goswami, Rupam; Bhowmick, Brinda

doi:10.1109/ted.2016.2631532

Cited by 38 publications

(23 citation statements)

References 20 publications

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“…As the N S increases, L 2 is increased [as given in (13)] which causes the reduction of C gd as indicated in (19) [22]. On the other hand, the C gs is increased with the increase of N S due to increase in depletion capacitance as verified from (17).…”

Section: Modelling Of Charge and Terminal Capacitancesmentioning

confidence: 87%

“…Double-gate TFETs [7], heterojunction TFETs [8], nanowire TFETs [9], gate all around TFETs [10,11], III-V TFETs [12], dual-metal-gate TFETs [13], gate-on-source only TFET [14] and L-shaped TFET [15] are some of the most key forms of TFETs. Many analytical models have been proposed until now to analyse the DC characteristics of TFETs [16][17][18][19]. The switching speed in circuits is strongly dependent on device capacitance, more specifically gate capacitance [20].…”

Section: Introductionmentioning

confidence: 99%

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Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

Mitra

Bhowmick

2018

Micro & Nano Letters

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A surface potential-based analytical capacitance model is proposed for gate-on-source-channel silicon on insulator (SOI) tunnel field effect transistor (GOSC TFET). The capacitance in the GOSC TFET is evidently shared by the gate-to-source capacitance which reduces the miller capacitance and leads to better switching speed in the circuit application. The effect of drain voltage, gate voltage, gate oxide thickness and source doping on the capacitance has been analysed in detail. The good matching between the modelled and Technology Computer-Aided Design (TCAD) simulated surface potential leads to the accurate calculation of capacitance. The validation of the capacitance model is done by comparing the model result with the simulation result and a good agreement between them validates the model formulation.

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Section: Modelling Of Charge and Terminal Capacitancesmentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

Mitra

Bhowmick

2018

Micro & Nano Letters

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“…The characteristic analysis and structure optimization of the gate dielectric material [13][14][15] and gate dielectrics with different dielectric constants have been performed [15][16][17][18][19][20]. In device physics, the analytical modeling of TFETs with the double-gate structure [21][22][23][24][25][26][27] and surrounding-gate structure [28][29][30][31][32][33] has also been extensively performed. One disadvantage of silicon-based TFETs compared to MOS-FETs is the smaller forward current, and the magnitude of the forward current is determined by the efficiency of the tunneling current generation.…”

Section: Introductionmentioning

confidence: 99%

A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

Jin

Wang

et al. 2021

Nanoscale Res Lett

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A bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

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“…Various structures of TFETs have been reported in the literatures with different materials and designs. Some of the remarkable forms of TFETs are circular Gate TFET, 3 nanowire TFETs, 4,5 heterojunction TFETs, 6 and double‐gate (DG) TFET 7,8 …”

Section: Introductionmentioning

confidence: 99%

An analytical model of surface potential and capacitance in heterojunction SELBOX TFET

Ghosh

Bhowmick

2021

Int J Numerical Modelling

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The Surface potential model based on 2D Poisson's equation of heterojunction Selective Buried Oxide (SELBOX) TFET has been predicted with appropriate boundary conditions in the rectangular coordinates. The device has been bifurcated into rectangular regions to perform an analysis of the electrostatic potential of the device. The potentials in the source and drain regions have been considered constant. The potential model is utilized to derive the mathematical relations for the electric field. Moreover, the affectability of drain voltage and gate voltage on capacitance has been explored by formulating the analytical model for capacitance. The charge model has also been articulated. The capacitance model considers depletion capacitances, inversion capacitances, and fringing capacitances of the proposed device. The total charge is modeled by considering the depletion charge and inner fringing charge at the source region with the dominancy of inversion charge at the channel region. Further, subthreshold swing (SS) based on band to band tunneling (BTBT) has been derived. The device behavior has been studied by incorporating quantum correction (QC). The analytically modeled results agree well with the TCAD simulation results.

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An Analytical Model of Drain Current in a Nanoscale Circular Gate TFET

Cited by 38 publications

References 20 publications

Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

An analytical model of surface potential and capacitance in heterojunction SELBOX TFET

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