Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
DOI: 10.1109/iccd.2001.955069
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An analytical model for trace cache instruction fetch performance

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Cited by 5 publications
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“…Agarwal et al describe in [30] an algorithm based on a twostate Markov chain. The first state produces sequential memory references and the second state generates random references.…”
Section: Related Workmentioning
confidence: 99%
“…Agarwal et al describe in [30] an algorithm based on a twostate Markov chain. The first state produces sequential memory references and the second state generates random references.…”
Section: Related Workmentioning
confidence: 99%