An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits

Ryu, Koungmin; Lee, Kil-Hoon; Lim, Jung-Pil; Kim, Jinho; Pae, Hansu; Park, Junho; Lim, Hyun‐Wook; Lee, Jae-Youl

doi:10.1109/tvlsi.2020.3018794

Cited by 4 publications

(2 citation statements)

References 15 publications

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“…Figure 10 shows PHY and EMT block diagram. Bangbang CDR, which is suitable for high jitter tolerance, 13,14 includes a circuit for horizontal margin measurement during EMT operation. Unlike eye open monitor (EOM), which measures horizontal eye margin using a phase interpolator, 15,16 EMT measures horizontal eye margin by generating jitter using VCO frequency modulation.…”

Section: An On-chip Emtmentioning

confidence: 99%

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

et al. 2023

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This paper proposes a 6Gb/s receiver for 8K displays and beyond. In the proposed receiver, a novel channel coding with 1.96% overhead is presented to guarantee minimum run-length in the clock embedded interface. It can also reduce bandwidth for effective data transmission compared to 9b/10b coding that requires 11.11% overhead. Furthermore, we present an on-chip eye margin tester that can measure the internal timing margin of receiver with only 1% area overhead. The prototype ICs are implemented using 0.18-μm HVCMOS process and evaluated in an 8K 65-in. panel.

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Section: An On-chip Emtmentioning

confidence: 99%

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

et al. 2023

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“…On the other hand, jitter is the time deviation of an event (usually the rise or fall event in digital systems and clocks) from an ideal reference time frame or sampling point (Da Dalt and Sheikholeslami, 2018). In digital transmission systems, increasing transfer rates are limited by mistiming in regeneration processes (Ryu et al, 2020). For this reason, ultra-low jitter clocks must be implemented to meet the tolerance ranges of transmitting and receiving equipment (Choi et al, 2019).…”

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confidence: 99%

Low-Timing-Jitter and Low-Phase-Noise Microwave Signal Generation Using a VCSEL-Based Optoelectronic Oscillator

et al. 2021

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This article presents the first results of the timing-jitter characterization of a VCSEL-based optoelectronic oscillator (VBO) at 2,5GHz. For all implementations, vertical-cavity surface-emitting lasers (VCSEL) emitting in the O and C-bands were characterized. The resonant cavity was modified through the optical delay line length to verify its impact on timing-jitter and phase noise of the VBO. The lowest peak-to-peak jitter value obtained experimentally was 71 mUI when the optical fiber length was 1 km, whereas the lowest phase noise was -124 dBc/Hz with 5 km. This phase noise value, measured at 10 kHz offset, represents an 8 dB improvement compared to previous results, and it is the lowest value reported in the literature for the VBO architecture at 2,5GHz.

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Evaluation of multi-level Bang–Bang phase detector with metastability effect using Markov chain

Salem

Saneei

Abbasi‐Moghadam

2021

Microelectronics Journal

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An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits

Cited by 4 publications

References 15 publications

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

Low-Timing-Jitter and Low-Phase-Noise Microwave Signal Generation Using a VCSEL-Based Optoelectronic Oscillator

Evaluation of multi-level Bang–Bang phase detector with metastability effect using Markov chain

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