An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

Ghosh, Prahlad C.; Haldar, Subhasis; Gupta, R. S.; Gupta, Mridula

doi:10.1016/j.mejo.2011.10.001

Cited by 73 publications

(35 citation statements)

References 30 publications

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“…This GAA structure shows better controllability of the MOSFET structure by controlling the gate voltage in a better way as compared to the previously manufactured devices [5][6][7]. As the complete silicon pillar is surrounded by the metal gate, so the controllability of the device increases.…”

Section: Introductionmentioning

confidence: 88%

An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology

Ghosh

Bhulania

Kumar

2015

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)

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This paper presents the analytical modeling of Gate All Around MOSFET using the Poisson's equation. Gate All Around MOSFET is experimentally demonstrated using a silicon channel. The analyzed model shows the close agreement with the simulation results. Atlas-3D tool has been used for the numerical simulations. A good performance has been achieved by scaling of the channel length to 50 nm with top-down approach. Our designed MOSFET follows the traditional MOSFET behavior inspite of enormous scaling and negligible hot carrier effects. The proposed model gives the simplest analysis in comparison to quantum models. Leakage current is negligible due to the use of bulk substrate which easily suppressed the adverse effect of parasitic capacitance. Simulated graph strongly follows the parabolic equation along the channel region for surface potential.

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Section: Introductionmentioning

confidence: 88%

An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology

Ghosh

Bhulania

Kumar

2015

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)

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“…Where μ 0 is electron mobility with its value taken to be μ 0 = 677 cm 2 /V s, the values of the parameters S = 350, N ref = 3 × 10 22 m −3 and high field saturation velocity v sat = 10 7 cm/s is considered as given in [37].…”

Section: Drain Current Model Including Mobile Charge Carriersmentioning

confidence: 99%

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

Sarkar

De²,

Dey

et al. 2012

J Comput Electron

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We report a systematic, quantitative investigation of analog and RF performance of cylindrical surroundinggate (SRG) silicon MOSFET. To derive the model, a pseudotwo-dimensional (2-D) approach applying Gauss's law in the channel region is extended for the cylindrical SRG MOSFET. Based on surface potential approach, expressions of drain current and differential capacitances are obtained analytically. Analog/RF figures of merit of SRG MOSFET are studied, including transconductance efficiency g m /I d , intrinsic gain, output resistance, cutoff frequency f T , maximum oscillation frequency f max and gain bandwidth product GBW. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modeled predictions have been extensively compared with the simulated characteristics obtained from the ATLAS device simulator and a nice agreement is observed with a wide range of geometrical parameters.

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“…At the same time, dual-material gate (DMG) devices have been theoretically studied [9][10][11][12][13][14][15][16] and fabricated [17][18][19]. Gate engineering technique such as dual metal gate (DMG) MOSFET has been firstly proposed in which the structure has two gates with different work functions [20].…”

Section: Introductionmentioning

confidence: 99%

Improved performance of nanoscale junctionless transistor based on gate engineering approach

Wang

Shan

Dou

et al. 2015

Microelectronics Reliability

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An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

Cited by 73 publications

References 30 publications

An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology

An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

Improved performance of nanoscale junctionless transistor based on gate engineering approach

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