An Analog CMOS Voltage-Controlled Phase-Shifter With A 100° Tuning Range For Telecommunication Baseband Signal Processing

Abstract

In order to correct phase non-linearities due to High Power Amplifiers (HPA) operating near saturation in telecommunication transceivers, a voltage-controlled phase-shifter based on Differential Difference Current Conveyors (DDCC) and a tunable resistor were developed. In order to suit a large variety of HPAs with broad phase non-linearities, the circuit's tuning capability has even been optimized up to an unprecedented 100 • while maintaining a good linearity (THD<-30 dB) and a gain close to 0 dB at 50 MHz. Designed in a 3.3 V 0.35 µm CMOS technology, the circuit current consumption ranges from 3.5 mA to 4.5 mA for a 50 MHz bandwidth, depending on the tuning range to be achieved. This paper describes the general architecture of the phase shifter as well as the inner structure of each implemented function and presents simulation results of the whole circuit.