An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs

Reliability analysis of a fault-tolerant RISC-V system-on-chip

“…As each of them uses different algorithms for evaluation, we selected the result based on the one more similar to the algorithm used in our work (i.e., sum of vectors). From [26], we selected the results the authors obtained running the Fibonacci algorithm. From [23], we selected the results from the execution of the Systest algorithm.…”

“…The authors of [24] present a technique applied at the processor microarchitecture level, protecting the register file through a combination of dual modular redundancy (DMR) and parity checking techniques. On the other hand, the authors of [26] developed a specific technique to protect the processor against SEUs in the FPGA configuration memory, specifically in ALU operations.…”

“…As shown in Table I, all analyzed works use the UART output or internal registers as a criterion for evaluating the propagation of errors, referring to the output of the benchmark algorithms executed in the processor. Only in [23], [24], and [26], the authors took into account the processor registers and presented a classification of the types of errors obtained. The methods used for the fault injection campaign in most works were based on simulation and emulation because they are low-cost approaches.…”

“…Ramos et al [26] presented a methodology to protect the processor ALU from faults in the FPGA configuration memory. The authors argue that it is not necessary to protect all ALU operations, but only the most common ones.…”

Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs

“…Under space radiation environments, soft-errors occur frequently on the configuration memory of FPGAs [6], [7], [8], as do dynamic random access memories (DRAMs) and static random access memories (SRAMs) [4], [5]. To decrease the frequency of soft-errors of the configuration memory, various scrubbing methods have been proposed that can refresh the configuration memory on an FPGA with a single configuration context [9], [10], [11], [12], [13].…”