An all‐digital phase‐locked‐loop with a robustness enhanced dual‐mode DCO

Abstract

An all‐digital‐phase‐locked‐loop (ADPLL) with a dual‐mode Class‐A/Class‐C Digital‐controlled‐oscillator (DCO) is presented in this letter. During the start‐up phase, the DCO operates in the Class‐A mode with increasing tail current. A low‐power amplitude‐to‐pulse‐converter (APC) is proposed to detect the oscillating amplitude of the DCO. After the start‐up, the DCO switches to the Class‐C mode with reduced tail current, resulting in better phase noise and lower power consumption. The ADPLL with the proposed DCO is implemented in a 65‐nm CMOS technology. The Class‐C mode DCO exhibits a phase noise of −123.3 dBc/Hz at 1‐MHz offset with a 2.7‐GHz carrier frequency. Measured results show about a 2.9‐dB phase noise improvement at 1‐MHz offset among the tuning range of 2.5–2.9 GHz, compared to the Class‐A DCO under the same power consumption. The figure‐of‐merit (FOM) and FOM including the tuning range (FOMT) of the DCO is 188.7 and 192.1, respectively. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:312–315, 2017