An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-&amp;#x00B5;m digital CMOS

Watanabe, Toshio; Terasawa, Tomohito

doi:10.1109/icecs.2009.5410979

Cited by 19 publications

(11 citation statements)

References 9 publications

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“…The all-digital construction gives T ADs superior environmental durability and reliability even in automotive engine compartments. We also reported the possibility of improving ADC performance along with the scaling of CMOS technologies [9], [10]. In addition, various investigators [11], [12] have also reported ADC methods for high-performance sensor interface circuits regarding delay line-based approaches, in other words, a time mode ADC method as well as the TAD concept.…”

Section: Introductionmentioning

confidence: 95%

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

Watanabe

Terasawa

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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An all-digital TAD-OFDM detection method for sensor interface with digital synchronous detection based on TAD (Time AID converter)-type ADC is introduced. A TAD basic structure is a completely digital circuit including a ring delay-line (RDL) with delay units (DUs) driven by an input voltage Vio and an RDL frequency counter, latch and encoder. Since the operating principle is to count the number of DUs through which the delay pulse passes within a sampling period T., this ADC (TAD) naturally performs as a Vio voltage integration circuit for T •. Hence, high frequency noises can be removed simultaneously with AID conversion. First, as an example of a voltage-integration effect as a low-pass tiIter, magnet pick-Up sensing was verified using a 22-bit TAD test chip fabricated using a 0.65-Jlm CMOS with 106 JlV/LSB (100 kS/s). Next, the idea of digital synchronous detection with TAD (called TAD-DSD with the voltage-integration effect) is proposed. Finally, by using the TAD-DSD principle, TAD OFDM detection is presented and experimentally confirmed, resulting in signal-detection of each wave-amplitude from a four-carrier-composite wave, which consists of frequencies, 1.6-, 3.2-, 6.4-and 12.8-MHz, respectively.

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Section: Introductionmentioning

confidence: 95%

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

Watanabe

Terasawa

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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“…So far, in order to overcome this problem, digital realization of ADCs (digital like ADCs) that can eliminate critical analog building blocks have been proposed. Several approaches include the comparator base switch-capacitor (CBSC) ADC [5], the fully digital (FA) ADC [6], and the time-mode ADC [7]. Each approach has its own merit by dealing with the fundamental limitations of analog circuits, yet has its own drawbacks as well.…”

Section: Introductionmentioning

confidence: 99%

An 8-bit 500kS/s semi-digital cyclic ADC with time-mode residue voltage generation

Hoseini

Lee

2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This work presents a semi-digital cyclic ADC with time-mode residue voltage generation. In the proposed scheme, the conventional switched-capacitor MDAC is replaced with a time-mode circuit which generates the residue voltage by controlling the charge and discharge interval of a capacitor. As a result, a semi-digital cyclic ADC can be realized using simple circuit components including capacitors, comparators, DC current source, and digital logics. Without the amplifier, the analog blocks can operate under a lower supply voltage that leads to reduced power consumption. Furthermore, a compact ADC can be realized by using small sized capacitors. An 8-bit, 500kS/s cyclic ADC is realized using CMOS 0.35µm technology, where the power consumption is 36.7μW.

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“…1(a) and 1(b) in the time-domain processing as follows. When received pulse signals are becoming high enough, the TAD-type TDC [7] (or other types of TDC [8], [9]) can be used to directly and simply digitize a time interval, which is represented with a start-pulse (Start-P) and a stop-pulse (Stop-P) corresponding to the round-trip time of pulse/wave signals. On the other hand, in case of low-level signals received, the TAD-type ADC is available for integrating their noisy signal waveform with a moving-average filtering effect [5], simultaneously with A/D conversion, resulting in highly-durable high-precision recognition of the signal-pulse/wave position using high-speed ADC sampling clocks (CKs).…”

Section: Introductionmentioning

confidence: 99%

“…CONCEPT OF TIME-MEASUREMENT CIRCUIT Fig. 1 illustrates a time-measurement circuit concept with three major sections: 1) an analog front-end part with conventional amplifier (amp) and comparator (com) for generating input pulse/wave signals for ADC/TDC input terminals, 2) time-domain processors with TAD-type ADC/TDC [7], 3) a digital back-end part for processing ADC/TDC data to compensate for conversion accuracy over a wide temperature range, by digitally comparing with reference values, for example. This concept can be adaptable to variable received-signal levels with a two-way method in Fig.…”

Section: Introductionmentioning

confidence: 99%

All-Digital A/D converter TAD for sensor interface over wide temperature ranges

Watanabe

Isomura

Terasawa

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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For achieving a highly-durable sensor ASIC with high performance and low cost, an all-digital sensor ADC using a time-domain processor TAD (Time A/D converter) is presented. Generally, measuring travel time of signals (e.g., light pulses, radio and ultrasonic waves, etc.) should be done under various stringent conditions (i.e., high ambient temperature) in automobiles, heavy-machinery and resource exploration systems, for example. Therefore, to realize wide-range temperature durability, sensor ADC circuits should be fully-digital, including a ring-delay-line (RDL) driven by an input voltage V in for its power supply, along with an RDL frequency counter, latch and encoder. In this study, an ADC core is implemented with 0.26 mm 2 in a low-cost 0.35-μm digital CMOS applying our original 2-CKES (clock edge shift) method for higher resolution. When detecting low-level noisy signals received, a high-speed sensor ADC with a voltage resolution of 10.9 mV/LSB (6.5bit, 40MS/s) is available for integrating received pulse/wave amplitude to determine signal-travel time in a wide temperature range between -40 and 125°C. In addition, the all-digital architecture TAD is suitable for porting and scaling to another silicon technology with minimal IC design term and cost. As a scaling result, using a test-IC in a 0.18-μm digital CMOS, we have also experimentally confirmed its stable operations between -40 and 125°C with a smaller active area (0.044mm 2 ) and higher resolutions, resulting in 0.15mV/LSB (1MS/s).

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An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS

Cited by 19 publications

References 9 publications

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

An 8-bit 500kS/s semi-digital cyclic ADC with time-mode residue voltage generation

All-Digital A/D converter TAD for sensor interface over wide temperature ranges

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