An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

Bae, Jun-Hyun; Seo, Jin‐Ho; Yeo, Hwanseok; Kim, Jae-Whui; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/cicc.2007.4405755

Cited by 14 publications

(16 citation statements)

References 3 publications

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“…However, achieving high-frequency operation is difficult because of the requirement for frequency multiplication. In addition, conventional DLLs [2][3][4]6,8,[10][11][12][13][14] only consider the design of the 90 • phase shifter; per-pin deskew is not supported in these DLLs.…”

Section: Introductionmentioning

confidence: 99%

An area-efficient and wide-range digital DLL for per-pin deskew applications

Chung¹,

Yu²

2017

Turk J Elec Eng & Comp Sci

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Abstract:In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications.The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A test chip of the 0.042 mm 2 DLL and the 3-ps-adjustable-resolution phase shifters with a 0.0025 mm 2 per-channel area was implemented using a 90-nm CMOS process. Simulation resultsshow that the phase error of the 90• phase shifter at 1.6 GHz is 2.4• . The DLL and the phase shifter consume 3.4 mW and 0.31 mW, respectively, at 1.6 GHz.

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Section: Introductionmentioning

confidence: 99%

An area-efficient and wide-range digital DLL for per-pin deskew applications

Chung¹,

Yu²

2017

Turk J Elec Eng & Comp Sci

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“…In order to enlarge the data valid window in the DDR controller and device, DQS delayed by 90 • phase shift to the center of the data period by the DDR controller generally. Many delay-locked loops (DLLs) and phase shifters have been proposed to provide the 90 • phase-shift clock or DQS required to transfer data correctly in the high-speed DDR memory controller [2,3,4]. In the physical implementation, the phase shifters may have long wire distance from DLL.…”

Section: Introductionmentioning

confidence: 99%

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications

Sheng

Chung

Lee

2010

IEICE Electron. Express

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Abstract:A fast-lock and portable all-digital delay-locked loop (AD-DLL) with 90 • phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3 • at 400 MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).

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“…A high linearity PWCL that employs a linear control stage and a digitally controlled charge pump is proposed for extending the range of both input and output duty cycles over a wide frequency range [1]. However, an analog PWCL usually requires a large on-chip capacitor that occupies a large chip area.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, in some applications, the DCC is combined with delaylocked loop (DLL) located on the output side [11] to eliminate the phase error caused by the DCC circuit. A conventional analog PWCL [1] uses a feedback approach to adjust the duty-cycle of the input clock.…”

Section: Introductionmentioning

confidence: 99%

“…To resolve this problem many approaches to correct the duty-cycle error and meet system requirements are presented. For example, an analog pulse-width control loop (PWCL) [1], an all-digital PWCL [6], and an alldigital duty-cycle corrector (ADDCC) [9]. In addition, in some applications, the DCC is combined with delaylocked loop (DLL) located on the output side [11] to eliminate the phase error caused by the DCC circuit.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An Efficient NAND Gate Based Glitch-free All-Digital Duty-Cycle Corrector Architecture

Theivanayaki¹,

Sathiskumar²

2015

International Journal of Advanced Research in Computer and Comm

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Duty-cycle correctors are widely used in high-speed devices and system-on-a-chip applications. Because both the positive and negative edges of the clock are utilized for sampling the input data, these systems require an exact 50% duty cycle of the input clock. However, as the clock signal is distributed over the entire chip with clock buffers, the duty cycle of the clock is often far from 50%. Because of the unbalanced rise and fall times, as a result of variations in process, voltage, and temperature. To resolve this problem and to correct the duty-cycle error many approaches are presented. In this work, wide-range NAND gate based glitch-free all-digital duty-cycle corrector is presented. The proposed NAND gate based glitch-free ADDCC not only achieves the desired output/input phase alignment, but also maintains the output duty cycle at 50% with a short locking time. In addition, the proposed method can mitigate the delay mismatch problem and produce minimum delay without any glitch. The circuit complexity also is reduced in the proposed NAND gate based ADDCC. The simulation is carried out in 0.65 nanometer CMOS process. An experimental result shows that the power consumed, delay and area is reduced in the proposed architecture. Simulation results are obtained using MODELSIM 6.3f. The power, area and delay are obtained using the XILINX ISE 8.1 software.

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An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

Cited by 14 publications

References 3 publications

An area-efficient and wide-range digital DLL for per-pin deskew applications

An area-efficient and wide-range digital DLL for per-pin deskew applications

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications

An Efficient NAND Gate Based Glitch-free All-Digital Duty-Cycle Corrector Architecture

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