An Algorithm for the Search of a Low Capacitor Count DAC Switching Scheme for SAR ADCs

Pilipko, Mikhail M.; Morozov, Dmitry V.

doi:10.1109/tcad.2020.2983132

Cited by 3 publications

(5 citation statements)

References 12 publications

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“…A novel LSB-frst algorithm [94] has reduced the power consumption to 60.8 nW and enhanced the linearity (SFDR) to 70.6 dB, as presented in Table 7, in 65 nm CMOS technology. Likewise, the proposed modifed algorithm [100] has diminished the power consumption of SAR ADC to 318.2 nW.…”

Section: Fom W � P Adcmentioning

confidence: 96%

“…Furthermore, the CDAC reference voltage switching schemes can decrease the power supply voltage and increase the speed of the conversion process . Moreover, the diferent algorithm schemes can diminish the number of iterations for the conversion process [90][91][92][93][94][95][96][97][98][99][100]. In addition, the SAR ADC architecture is suitable for fne CMOS processes [101].…”

Section: Sar Adc Architecturementioning

confidence: 99%

“…Terefore, the number of bit cycles for conversion is determined by N cycle iteration by N resolution of SAR ADC. A diferent algorithm called the prediction algorithm [93][94][95][96][97][98][99][100] has been adopted to achieve power consumption savings and reduce the N cycle iterations. In the prediction algorithm, advanced information on the sampled value may be detected by a controlled SAR logic register [93].…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

“…A minimum possible amount of capacitor count is attained in [100]. Tis algorithm searches for fractions of charge in a charge-sharing DAC and produces a solution based on the smallest possible number of unit capacitors.…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

“…Also, the LSB capacitor technique [47], the dual split CDAC array technique [34], and the chargesharing scheme with a switched capacitor (SC) integrator [63] achieve 4.1 nW, 110 nW, and 280 nW, respectively. Moreover, the timing control adaptive window [96], a novel LSB-frst algorithm [94], and the modifed algorithm with a minimum possible amount of capacitor count [100] accomplish 74 nW, 60.8 nW, and 318.2 nW, respectively. Furthermore, the main structures of the building blocks of SAR ADC, including a bootstrap switch, a two-stage dynamic latch comparator, and a two-stage subarray capacitor technique with fully diferential [5] or single-ended [11], obtained 306 nW and 250 nW, respectively.…”

Section: Fom W � P Adcmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Fom W � P Adcmentioning

confidence: 96%