An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

Trakimas, Michael; Sonkusale, Sameer

doi:10.1109/tcsi.2010.2092132

Cited by 126 publications

(64 citation statements)

References 20 publications

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“…A capacitive DAC structure based on charge sharing principle was used in [9] which generate the varying comparison interval. A hybrid switched-capacitor/resistor-string architecture was used for implementing DAC in [10] [12]. The 2 DACs used in this architecture create the threshold levels which bound the input signal from above and below.…”

Section: Previous Literaturementioning

confidence: 99%

“…Level crossing ADCs offers lower sampling rate, power consumption and area than synchronous ADCs. Level crossing ADC has been mainly used in embedded sensing systems, such as environmental sensors (temperature, pressure sensors), implantable biomedical applications, hearing aids and ultrasound applications [2]- [7], [10], [ 11]. This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors and additional dummy NMOS devices for a level crossing ADC.…”

Section: Introductionmentioning

confidence: 99%

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Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Antony¹

2018

IJRASET

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This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors suitable for an asynchronous level crossing ADC. Dummy NMOS devices are added to the 1 bit DAC for reducing the charge accumulation and clock feed through giving a 81.26 % increase in SFDR for 5 kHz input frequency compared to the 1 bit DAC with only pseudo resistors. The asynchronous control logic for the DAC is designed digitally and optimized for lower power consumption. The DAC and its control logic has been designed using 180nm technology in cadence using a supply voltage of 0.8 V and consumes an average power of 2.323 nW. Keyword: Digital to Analog Converters (DAC), Analog to Digital Converters (ADC), Asynchronous, Level crossing, pseudo resistors I. INTRODUCTIONAsynchronous ADC architectures are emerging as an excellent alternative for replacing synchronous ADCs in various applications such as portable and implantable biomedical signal sensing devices, remote environmental monitors and sensors, military applications, magnetic disk reader, optical disk readers and wireless applications such as audio devices and cellular telephones. The advantages of asynchronous circuits compared to their synchronous counter parts are higher speed, lower power consumption, and smaller area, immunity to metastable behaviour, less clock skew and low susceptibility to electromagnetic interference. Level crossings ADCs are asynchronous ADCs that generate output samples only when the input signal crosses a threshold level [1]. Level crossing ADCs offers lower sampling rate, power consumption and area than synchronous ADCs. Level crossing ADC has been mainly used in embedded sensing systems, such as environmental sensors (temperature, pressure sensors), implantable biomedical applications, hearing aids and ultrasound applications [2]- [7], [10],[ 11]. This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors and additional dummy NMOS devices for a level crossing ADC. A digital DAC logic using gates and latches for the control of the 1 bit DAC asynchronously is also designed in this paper. In this paper, section II discusses previous literatures on DAC used in level crossing ADCs. Section III gives the circuit implementation followed by results and discussion in section IV. Section V gives the conclusion of the paper.

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Section: Previous Literaturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Antony¹

2018

IJRASET

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“…Accordingly, no data are fed through to higher levels in the system, allowing these to remain idle. These possibilities in the design of sensor front ends have been explored for ultrasound measurement systems [22] as well as for other energy constrained sensor applications [23]. In terms of energy cost, the A/D conversion is dominant in the scenarios discussed above.…”

Section: B Low Power Analog Front End Architecturementioning

confidence: 99%

Concepts and architecture for a thumb-sized smart IoT ultrasound measurement system

Delsing

Deventer

Eliasson

et al. 2016

2016 IEEE International Ultrasonics Symposium (IUS)

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Abstract-This paper presents the technology concepts for a "thumb"-sized self-contained ultrasonic IoT measurement system. An overall architecture is proposed, and key elements are discussed with solutions using existing technology, thus arguing that realization is possible with the current technology.Such an ultrasonic IoT measurement system is constrained by its size and available energy, although it requires at least decent computational and communication resources. Because streaming data from such a device is not advisable from an energy viewpoint, there is a need for resource efficient (energy, memory and computational power) data analysis.An architecture with the following parts as well as some implementation details and performance data are proposed here:• Energy supply, battery and super capacitor • Transducer excitation achieving almost zero electrical losses • Event detection sensor interface • Data aggregation using sparse approximation and learned feature dictionaries, adapted to resource constrained embedded systems • IoT communication protocols and implementations enabling event -based communication and System of Systems integration capabilities The optimization of system level performance requires each subsystem to be optimized for the specific measurement situation taking into account the subsystem interdependencies. This can be performed using a combined electrical and acoustical model of the system. Here, the model allowing electronic and acoustic co-simulation using SPICE is an important tool bridging the electronic and acoustic domains.

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“…The conventional sampling is replaced with asynchronous mapping of analog signal value into the time domain. Existing implementations use a level-crossing sampling [14][15][16][17][18], asynchronous Sigma-Delta modulator [6,7], or a hybrid approach [8,19]. The A-ADCs based on the levelcrossing sampling [20,21] are the instantaneous value converters, while the A-ADCs with TEMs serve as the mean value converters due to inherent integration properties [6].…”

Section: Asynchronous Adcsmentioning

confidence: 99%

Time-to-digital converters based on event-driven successive charge redistribution: A theoretical approach

Kościelnik

Miśkowicz

2012

Measurement

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An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

Cited by 126 publications

References 20 publications

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Concepts and architecture for a thumb-sized smart IoT ultrasound measurement system

Time-to-digital converters based on event-driven successive charge redistribution: A theoretical approach

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