An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning

Chen, Jianli; Liu, Yan; Zhu, Ziran; Wang, Zihao

doi:10.1016/j.vlsi.2017.03.006

Cited by 34 publications

(5 citation statements)

References 18 publications

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“…Using memetic algorithms for optimization [27] is also associated with long-term local searches and requires further study.…”

Section: Discussionmentioning

confidence: 99%

“…In [27], to efficiently optimize a multi-objective thermally aware nonslicing floor planning method, an adaptive hybrid memetic algorithm was presented to optimize the area, total wirelength, and maximum and average temperatures of a chip. In [27]'s proposed algorithm, a genetic search algorithm is used as a global search method to explore the search space as much as possible. A modified simulated-annealing search algorithm is used as a local search method to exploit the information in the search region.…”

Section: Literature Reviewmentioning

confidence: 99%

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Hybrid genetic‐paired‐permutation algorithm for improved VLSI placement

et al. 2020

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This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies.The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N 2 ).

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“…Using memetic algorithms for optimization [27] is also associated with long-term local searches and requires further study.…”

Section: Discussionmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 99%

Hybrid genetic‐paired‐permutation algorithm for improved VLSI placement

et al. 2020

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“…In [14], an algorithm based on simulated annealing was designed to obtain efficient floorplans with minimum peak temperature. Since the primary objective is peak temperature, it could have minimized area and wire length.…”

Section: Introductionmentioning

confidence: 99%

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

et al. 2023

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In VLSI circuit design, physical design is one of the main steps in placing the circuit into the chip area. Floorplanning is a crucial step in the physical design of IC design, which generates a blueprint for the placement of circuit modules into the chip. A floorplanning step accepts a netlist as its input, given by the circuit-partitioning step of physical design. The floorplanning step generates optimal placements for the circuit modules. The netlist contains the modules' dimensions, size, and interconnect information. During the floorplan generation, the chip area, wire length required for connecting modules and the heat generated by the chips can be estimated. A good floorplan makes placements and routing simple. In order to improve the circuit performance by minimizing chip area, wire length, and peak temperature, it is essential to generate an optimized floorplan by developing metaheuristic optimization algorithms. A novel Hybridized Multicriteria Ant Colony and Firefly Optimization (HMAC-FO) technique is introduced to generate an optimized floorplan. The primary focus of HMAC-FO technique is to design a model for generating efficient floorplanning. The standard MCNC benchmark dataset has a number of modules with their connections. Firefly optimization is the main algorithm in HMAC-FO, which has been used in generating efficient floorplan with the optimized area, wire length and thermal. The firefly algorithm initially requires some number of solutions as the fireflies' population. In the firefly algorithm, usually, the populations are generated randomly. But, to improve the firefly optimization algorithm's performance and obtain better optimum results, the proposed technique uses ACO to generate the initial population, which are all optimal solutions. The firefly algorithm uses the set of optimal solutions as the initial population and generates the globally optimal result. The proposed technique has experimented with the standard MCNC benchmark circuits, and the results prove that the proposed algorithm reduces the area by 3.48%, the wire length by 0.64% and the temperature by 3.33% than the best existing methodology. The proposed methodology generates a good floorplan with all the required optimization, such as area, wire length and heat generation.

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“…For efficient floorplans with lesser peak temperature, a genetic search algorithm and modified simulated annealing search algorithm were designed in [11]. A Genetic algorithmic program (GA) with harmony search algorithm was presented in [12] to lessen space and wire length.…”

Section: Introductionmentioning

confidence: 99%

Splay Tree Hybridized Multicriteria ant Colony and Bregman Divergencive Firefly Optimized Vlsi Floorplanning

Balakrishnan

Venkatesan

2021

Preprint

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Floorplanning is a basic designing step in VLSI circuit to estimate chip area before the optimized placement of digital blocks and their connections. The process of Floorplanning involves identifying the locations, shape, and size of components in a chip. The floorplanning is a hard problem since the consumption of energy and heat generation was high for the placement of modules. In order to improve the optimized floor planning, a novel Splay tree Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly Optimized Floor Planning (STHMAC-BDFOFP) technique is proposed. Main objective of STHMAC-BDFOFP technique is to efficient floor planning with minimum time. Initially, a number of modules are given with their connections obtained from benchmark dataset. In STHMAC-BDFOFP, a Splay tree-based non-slicing floor planning model constructing trees via modeling geometric relationship among modules. A splay tree is build after performing different operations namely splaying, join, split, insertion, and deletion on modules for floor planning. The constructed floorplan design is optimized by Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly algorithm. At first, the ant colony optimization is applied for finding the local optimum solution from the population of modules in the Splay tree with Multicriteria functions namely energy consumption, heat generation, space occupied, and wire length. Depends on fitness measure, the local optimum solution is determined. Then the global solution is attained by applying the Bregman Divergencive Firefly ranked algorithm. In this way, optimum modules in the splay tree are identified and obtain efficient floorplanning in VLSI design. Discussed results indicate that STHMAC-BDFOFP technique improves the performance of energy and heat aware floor planning as compared to conventional works.

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An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning

Cited by 34 publications

References 18 publications

Hybrid genetic‐paired‐permutation algorithm for improved VLSI placement

Hybrid genetic‐paired‐permutation algorithm for improved VLSI placement

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

Splay Tree Hybridized Multicriteria ant Colony and Bregman Divergencive Firefly Optimized Vlsi Floorplanning

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