An Adaptive and Universal Timing Mismatch Estimation Method for TIADCs

Sun, Libin; Zhang, Zhenwei; Lang, Lili; Kang, Tong; Xiong, Wei; Lei, Yu; Zhong, Wanxie; Dong, Yong

doi:10.1109/tvlsi.2023.3288822

Cited by 3 publications

(1 citation statement)

References 14 publications

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“…Background calibration refers to when the ADC is calibrated while working, but it takes a period of time to converge. The algorithms reported in [18,19] have quite a fast convergence speed; however, they are ineffective at certain frequencies and can even deteriorate the ADC performance due to its own defects, whereas the digital background calibration algorithms in [20][21][22][23][24][25] do require the external input injection, such as a pseudorandom (PN) noise sequence [20][21][22][23] and sinusoidal signals [24] for calibration, which typically have convergence speeds in the order of approximately 10 6 to 10 8 cycles [20][21][22][23], 10 5 cycles, and 10 4 cycles [25]. Compared with the background calibration, the foreground one is much more reliable.…”

Section: Introductionmentioning

confidence: 99%

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

Zhang,

Hu,

Lang

et al. 2024

Electronics

Self Cite

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A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

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Section: Introductionmentioning

confidence: 99%

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

Zhang,

Hu,

Lang

et al. 2024

Electronics

Self Cite

View full text Add to dashboard Cite

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Frequency-domain Compensator Design of Frequency Response Mismatch in the Broadband Quadrature Reception System

Meng,

Ye,

Zhao

et al. 2024

2024 Ieee Autotestcon

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A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters

Sun,

Lang,

Zhong

et al. 2023

Electronics

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This paper proposes a fully digital background calibration method for time-interleaved analog-to-digital converter (TIADC) mismatches. The method analyzes the frequency and phase of spurious signals caused by three types of mismatches in TIADCs in the frequency domain. By utilizing the Hilbert transform and frequency shifting, orthogonal basis signals located at the mismatch frequencies can be constructed. The calibration of mismatches is achieved by linearly combining the orthogonal basis signals with the estimated coefficients and subtracting them from the original signal. The estimation of coefficients is determined by evaluating the correlation between the linear combination of orthogonal basis signals and the calibrated signal. Furthermore, an exponential moving average (EMA) and least mean square (LMS) algorithm are introduced to expedite the coefficient estimation process. The entire calibration process converges in merely 600 samples, significantly improving the convergence speed. By monitoring the amplitude of the input signal and adjusting the LMS step, the algorithm is functional under different amplitude signals, enhancing the robustness. An off-chip calibration is conducted based on a commercial 14-bit, 8-channel, 2.4GSPS TIADC. Results indicate that all spurious signals are suppressed below 80 dB, and the convergence rate is consistent with the simulation.

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An Adaptive and Universal Timing Mismatch Estimation Method for TIADCs

Cited by 3 publications

References 14 publications

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

Frequency-domain Compensator Design of Frequency Response Mismatch in the Broadband Quadrature Reception System

A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters

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